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| preliminary technical data mixed-signal control processor with arm cortex-m4 and 16-bit adcs adsp-cm402f / cm403f/cm407f / cm408f / cm409f rev. prf information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2014 analog devices, inc. all rights reserved. system features up to 240 mhz arm cortex-m4 with floating-point unit 24-channel analog front end (afe) with 16-bit adcs 128k byte to 384k byte zero-wait-state l1 sram with 16k byte l1 cache up to 2m byte flash memory single 3.3 v power supply package options: 176-lead (24 mm 24 mm) lqfp package 120-lead (14 mm 14 mm) lqfp package 212-ball (19 mm 19 mm) bga package static memory controller (smc ) with asynchronous memory interface that supports 8-bit and 16-bit memories enhanced pwm units four 3 rd /4 th order sinc filters for glueless connection of sigma-delta modulators hardware-based harmonic analysis engine 10/100 ethernet mac full speed usb on-the-go (otg) two can (controller area network) 2.0b interfaces three uart ports two serial peripheral interface (spi-compatible) ports eight 32-bit general-purpose timers four encoder interfaces, 2 with frequency division analog front end two 16-bit sar adcs with up to 24 multiplexed inputs, supporting dual simultaneous co nversion in 380 ns (16-bit, no missing codes) adc controller (adcc) and dac controller (dacc) two 12-bit dacs two 2.5 v precision voltage reference outputs (for details, see adc/dac specifications on page 66 .) figure 1. block diagram up to 2m byte flash (executable) l1 cache 16k byte l1 instruction cache system control blocks peripherals hardware functions l3 memory system fabric 1 emac with ieee 1588 (optional) 2x sport 2 can static memory controller async interface 2 spi 4 quadrature encoder 8 timer 12 pwm pairs 1 twi / i 2 c usb fs otg (optional) l1 memory up to 384k byte parity-enabled zero-wait-state sram jtag, swd, coresight? trace event control system watchdogs pll & power management fault management 3 uart adcc dacc harmonic analysis engine (hae) analog front end gpio (40 or 91) 2 adc 2 dac sinc filters security cortex-m4
rev. prf | page 2 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table of contents general description ................................................. 3 analog front end ................................................. 4 arm cortex-m4 core ........................................... 6 embeddedice ...................................................... 7 processor infrastructure ......................................... 7 memory architecture ............................................ 8 system acceleration ............................................ 10 security features ................................................ 10 processor reliability features ................................. 10 additional processor peripherals ............................ 11 clock and power management ............................... 14 system debug .................................................... 16 development tools ............................................. 16 additional information ........................................ 16 related signal chains .......................................... 16 adsp-cm40xf detailed signal descriptions ................ 17 adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions ............................................. 21 adsp-cm402f/adsp-cm403f general-purpose i/o multiplexing for 120-lead lqfp ....................... 26 adsp-cm407f/ADSP-CM408F 176-lead lqfp signal descriptions ............................................. 28 adsp-cm407f/ADSP-CM408F general-purpose i/o multiplexing for 176-lead lqfp ....................... 36 adsp-cm409f 212-ball bga signal descriptions ... ...... 39 adsp-cm409f general-purp ose i/o multiplexing for 212-ball bga ... .............................................. 47 adsp-cm40xf designer quick reference ................... 50 specifications ........................................................ 61 operating conditions ........................................... 61 electrical characteristics ....................................... 63 adc/dac specifications ...................................... 66 flash specifications .............................................. 72 absolute maximum ratings ................................... 73 esd sensitivity ................................................... 73 package information ............................................ 73 timing specifications ........................................... 74 processor test conditions ................................... 105 output drive currents ....................................... 105 environmental conditions .................................. 106 adsp-cm402f/adsp-cm403f 120-lead lqfp lead assignments ............................................. 108 adsp-cm407f/ADSP-CM408F 176-lead lqfp lead assignments ............................................. 111 adsp-cm409f 212-ball bg a ball assignments .. ........ 115 outline dimensions .............................................. 119 pre release products ............................................. 122 revision history 08/14revision pre to revision prf added adsp-cm409f model to adsp-cm40xf family prod- uct features ............................................................ 3 added package information in adsp-cm409f 212-ball bga signal descriptions ................................................. 39 added package information in adsp-cm409f general-pur- pose i/o multiplexing for 212-ball bga ...................... 47 updated specifications ............................................ 61 added package information in adsp-cm409f 212-ball bga ball assignments .................................................. 115 added 212-ball bga package dimensions in outline dimen- sions .................................................................. 119 added adsp-cm409f model in pre release products ... 122 preliminary technical data rev. prf | page 3 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f general description the adsp-cm40xf family of mixe d-signal control processors is based on the arm ? cortex-m4 tm processor core with floating- point unit operating at frequencies up to 240 mhz and integrat- ing up to 384kb of sram memory, 2mb of flash memory, accelerators and peripherals optimized for motor control and photo-voltaic (pv) inverter cont rol and an analog module con- sisting of two 16-bit sar-type adcs and two 12-bit dacs. the adsp-cm40xf family operates from a single voltage supply (vdd_ext/vdd_ana), generating its own internal voltage supplies using internal voltage re gulators and an external pass transistor. this family of mixed-signal cont rol processors offers low static power consumption and is produced with a low-power and low- voltage design methodology, delivering world class processor and adc performance with lower power consumption. by integrating a rich set of indu stry-leading system peripherals and memory (shown in table 1 ), the adsp-cm40xf mixed-sig- nal control processors are th e platform of choice for next-generation applications that require risc programmabil- ity, advanced communications and leading-edge signal processing in one integrated package. these applications span a wide array of markets including power/motor control, embed- ded industrial, instrumentation, medical and consumer. each adsp-cm40xf family memb er contains the following modules. ? 8 gp timers with pwm output ? 3-phase pwm units with up to 4 output pairs per unit ?2 can modules ? 1 two-wire interface (twi) module ?3 uarts ? 1 adc controller (adcc) to control on-chip adcs ? 1 dac controller (dacc) to control on-chip dacs ? 1 sinus cardinalis (sinc) filter ? 1 harmonic analysis engine (hae) ? 1 spi connected to in ternal spi flash memory ?1 watchdog timer unit ? 1 cyclic redundancy check (crc) table 1 provides the additional product features shown by model. table 1. adsp-cm40xf family product features generic adsp-cm402f adsp-cm403f ads p-cm407f ADSP-CM408F adsp-cm409f package 120-lead lqfp 176-lead lqfp 212-ball bga gpios 40 91 smc 16-bit asynchronous/5 addres s 16-bit asynchronous/24 address adc enob (no averaging) 11+ 13+ 11+ 13+ adc inputs 24 16 24 dac outputs 2 n/a 2 sports 3 half-sports 4 half-sports ethernet n/a 1 n/a n/a 1 n/a 1 usb n/a 1 1 n/a 1 1 1 external spi 1 2 hae 1 can 2 uart 3 feature set code efcefabdab a l1 sram (kb) 128 128 384 128 128 384 384 128 384 384 384 flash (kb) 512 256 2048 512 256 2048 2048 1024 2048 2048 2048 core clock (mhz) 150 100 240 150 100 240 240 150 240 240 240 model adsp-cm402bswz-ef adsp-cm402bswz-ff adsp-cm403bswz-cf adsp-cm403bswz-ef adsp-cm403bswz-ff adsp-cm407bswz-af adsp-cm407bswz-bf adsp-cm407bswz-df adsp-cm408bswz-af adsp-cm408bswz-bf adsp-cm409cbcz-af rev. prf | page 4 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data analog front end the processors contain two adcs and two dacs. control of these data converters is simplified by a powerful on-chip ana- log-to-digital conversion cont roller (adcc) and a digital-to- analog conversion controller (dacc). the adcc and dacc are integrated seamlessly into th e software programming model, and they efficiently manage the configuration and real-time operation of the adcs and dacs. for technical details, see adc/dac specifications on page 66 . the adcc provides the mechanis m to precisely control execu- tion of timing and analog sampling events on the adcs. the adcc supports two-channel (one eachadc0, adc1) simul- taneous sampling of adc inputs with tbd ps time offset accuracy (aperture delay), and can deliver 16 channels of adc data to memory in 3 s. conversion data from the adcs may be either routed via dma to memory, or to a destination register via the processor. the adcc can be configured so that the two adcs sample and convert both analog inputs simultaneously or at different times and may be operated in asynchronous or syn- chronous modes. the best performance can be achieved in synchronous mode. likewise, the dacc interfaces to two dacs and has purpose of managing those dacs. conversion data to the dacs may be either routed from memory th rough dma, or from a source register via the processor. functional operation and programming for the adcc and dacc are described in detail in the adsp-cm40xf mixed-sig- nal control processor with ar m cortex-m4 and 16-bit adcs hardware reference . adc and dac features and performance specifications differ by processor model. simplified block diagrams of the adcc, dacc and the adcs and dacs are shown in figure 2 and figure 3 . considerations for best converter performance as with any high performance analog/digital circuit, to achieve best performance, good circuit design and board layout prac- tices should be followed. the power supply and its noise bypass (decoupling), ground return paths and pin connections, and analog/digital routing channel paths and signal shielding, are all of first-order consideration. for application hints of design best practice, see figure 4 and the adsp-cm40xf mixed-signal con- trol processor with arm cortex -m4 and 16-bit adcs hardware reference . figure 2. cm402f/cm403f/cm409f analog front end block diagram dac1 dac0 adc0 adc1_vin00 . . . adc1_vin01 adc1_vin02 adc1_vin11 dac1 adc0_vin00 . . . adc0_vin01 adc0_vin02 adc0_vin11 dac0 mux mux adcc dacc control control micro controller dma sram memory data vref1 vref0 refcap buf buf buf buf buf buf dac1_vout dac0_vout ~ ~ ~ adc1 buf buf band gap adc/dac local controller preliminary technical data rev. prf | page 5 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f figure 3. cm407f/cm408f analog subsystem block diagram figure 4. typical powe r supply configuration 1 1 for more information abou t the vreg circuit, see figure 9 , internal voltage regulator circuit. dac1 dac0 adc1 adc0 adc1_vin00 . . . adc1_vin01 adc1_vin02 adc1_vin07 dac1 adc0_vin00 . . . adc0_vin01 adc0_vin02 adc0_vin07 dac0 mux mux adcc dacc control control micro controller dma sram memory data vref1 vref0 refcap buf buf buf buf buf buf ~ ~ not pinned out buf buf band gap adc/dac local controller vdd_ext vdd_vreg vdd_int byp_d0 gnd vdd_ana0 gnd_ana0 byp_a0 vref0 gnd_vref0 refcap gnd_vref1 vref1 byp_a1 gnd_ana1 vdd_ana1 vreg circuit 1 gnd_ana 3.3v connected at one point gnd_dig plane gnd_ana plane gnd_dig gnd_ana2 gnd_ana3 vreg_base adsp-cm40xf 0.01f 0.1f 10f 10f 0.1f 10f 0.1f 10f 0.01f 0.1f 10f 10f 0.1f 10f all labeled capacitors are ceramic capacitors. all labeled 10f capacitors are low esr capacitors. rev. prf | page 6 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adc module the adc module contains two 16-bit, high speed, low power successive approximat ion register (sar) adcs, allowing for dual simultaneous sampling with each adc proceeded by a 12-channel multiplexer. see adc specifications on page 66 for detailed performance specifications. input multiplexers enable up to a combined 26 analog inpu t sources to the adcs (12 ana- log inputs plus 1 dac loopback input per adc). the voltage input range requiremen t for those analog inputs is from 0 v to 2.5 v. all analog in puts are of single-ended design. as with all single-ended inputs , signals from high impedance sources are the most difficult to control, and depending on the electrical environment, may requ ire an external buffer circuit for signal conditioning ( figure 5 ). an on-chip pre-buffer between the multiplexer and ad c reduces the need for addi- tional signal conditioning external to the processor. additionally, each adc has an on -chip 2.5 v reference that can be overdriven when an external voltage reference is preferred. dac module the dac is a 12-bit, low power, string dac design. the output of the dac is buffered, and can drive an r/c load to either ground or v dd_ana . see dac specifications on page 68 for detailed performance specifications. it should be noted that on some models of the processor, the dac outputs are not pinned out. however, these outputs are always available as one of the multiplexed inputs to the adcs. this feature may be useful for functional self-check of the converters. arm cortex-m4 core the arm cortex-m4, core shown in figure 6 , is a 32-bit reduced instruction set computer (risc). it uses 32-bit buses for instruction and data. the length of the data can be eight bits, 16 bits, or 32 bits. the length of the instruction word is 16 or 32 bits. the controller has the following features. figure 5. equivalent single -ended input (simplified) analog source v in0 vdd_ana external buffer c ext r ext adsp-cm40xf hold to adc track 9pf 85 v in1 v in2 v inx 1.5pf mux pre-buffer 1.5pf 1.5pf 1.5pf preliminary technical data rev. prf | page 7 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f cortex-m4 architecture ? thumb-2 isa technology ? dsp and simd extensions ? single cycle mac (up to 32 32 + 64 -> 64) ? hardware divide instructions ? single-precision fpu ? nvic interrupt controlle r (129 interrupts and 16 priorities) ? memory protection unit (mpu) ?full coresight tm debug, trace, breakpoints, watchpoints, and cross-triggers microarchitecture ? 3-stage pipeline with branch speculation ? low-latency interrupt processing with tail chaining configurable for ultra low power ? deep sleep mode, dynamic power management ? programmable clock generator unit embeddedice embeddedice ? provides integrated on-chip support for the core. the embeddedice module contains the breakpoint and watch-point registers that allow code to be halted for debugging purposes. these registers are cont rolled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters debug state. once in a debug state, the proces- sor registers can be inspected as well as the flash/ee, sram, and memory-mapped registers. processor infrastructure the following sections provide information on the primary infrastructure components of the adsp-cm40xf processors. dma controllers (ddes) the processor contains 17 peripheral dma channels plus two mdma streams. dde channel nu mbers 0C16 are for peripher- als and channels 17C20 are for mdma. system event controller (sec) the sec manages the enabling and routing of system fault sources through its integrat ed fault management unit. trigger routing unit (tru) the tru provides system-level sequence contro l without core intervention. the tru maps trigge r masters (generators of trig- gers) to trigger slaves (receivers of triggers). slave endpoints can be configured to respond to triggers in various ways. common applications enabled by the tru include: ? initiating the adc sampling periodically in each pwm period or based on external events ? automatically triggering the start of a dma sequence after a sequence from another dma channel completes ? software triggering ? synchronization of concurrent activities figure 6. cortex-m4 block diagram 1 9 , & 1 ( 6 7 ( ' 9 ( & 7 2 5 ( ' , 1 7 ( 5 5 8 3 7 & 2 1 7 5 2 / / ( 5 $ 5 0 & 2 5 7 ( ; 0 ) 3 5 2 & ( 6 6 2 5 & 2 5 ( : , 7 + ) 3 8 ( 7 0 ( 0 % ( ' ' ( ' 7 5 $ & ( 0 $ & 5 2 & ( / / 0 3 8 0 ( 0 2 5 < 3 5 2 7 ( & 7 , 2 1 8 1 , 7 ' : 7 ' $ 7 $ : $ 7 & + 3 2 , 1 7 7 5 $ & ( ) 3 % ) / $ 6 + 3 $ 7 & + % 5 ( $ . 3 2 , 1 7 & 2 5 7 ( ; , 1 7 ( 5 1 $ / % 8 6 0 $ 7 5 , ; , 7 0 , 1 6 7 5 8 0 ( 1 7 $ 7 , 2 1 7 5 $ & ( 0 $ & 5 2 & ( / / $ 3 $ & & ( 6 6 3 2 5 7 ' 3 ' ( % 8 * 3 2 5 7 % 8 6 0 $ 7 5 , ; , 1 7 ( 5 5 8 3 7 $ 1 ' 3 2 : ( 5 & 2 1 7 5 2 / 6 : ' ' ( % 8 * , 1 7 ( 5 ) $ & ( ( 7 0 7 5 $ & ( , 1 7 ( 5 ) $ & ( , 7 0 7 5 $ & ( , 1 7 ( 5 ) $ & ( 3 3 % ' ( % 8 * % 8 6 , 1 7 ( 5 ) $ & ( 3 3 % 6 < 6 ' & 2 ' ( , & 2 ' ( rev. prf | page 8 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pin interrupts every port pin on the processor ca n request interrupts in either an edge-sensitive or a level-se nsitive manner with programma- ble polarity. interrupt functionality is decoupled from gpio operation. six system-level interrupt channels (pint0C5) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins . the assignment from pin to interrupt is not performed on a pin-by-pin basis. rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab le half-port assignment and interrupt management. this includes masking, identification, and clearing of requests. these re gisters also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address entries to write-one-to-set or write-one-to-clear them individually. general-purpose i/o (gpio) each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C a write one to mod- ify mechanism allows any combination of individual gpio pins to be mo dified in a single instruction, without affecting the level of any other gpio pins. ? gpio interrupt mask register s C allow each individual gpio pin to function as an interrupt to the processor. gpio pins defined as inputs ca n be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C specify whether indi- vidual pins are level- or ed ge-sensitive and specifyif edge-sensitivewhether just the rising edge or both the ris- ing and falling edges of th e signal are significant. pin multiplexing the processor supports a flexible multiplexing scheme that mul- tiplexes the gpio pins with various peripherals. a maximum of 5 peripherals plus gpio functionality is shared by each gpio pin. all gpio pins have a bypass path featurethat is, when the output enable and the input en able of a gpio pin are both active, the data signal before the pad driver is looped back to the receive path for th e same gpio pin. for more information, see: ? adsp-cm402f/adsp-cm403f general-purpose i/o multiplexing for 120-le ad lqfp on page 26 . ? adsp-cm407f/ADSP-CM408F general-purpose i/o multiplexing for 176-le ad lqfp on page 36 . ? adsp-cm409f general-purpose i/o multiplexing for 212-ball bga on page 47 . memory architecture the internal and external memory of the adsp-cm40xf processor is shown in figure 7 and described in the following sections. figure 7. adsp-cm40xf memory map 0 h p ; 6 3 , ) o d v k 0 % [ - 0 - - 2 2 e g i s t e r s " x & 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d # o r e 3 i g h t 2 / - + " ! 2 - 0 0 " $ e v i c e s + " ! s y n c - e m o r y " a n k - " ! s y n c - e m o r y " a n k - " ! s y n c - e m o r y " a n k - " ! s y n c - e m o r y " a n k - " 3 0 ) ! d d r e s s 3 p a c e - " 3 y s t e m - - 2 " i t " a n d ! l i a s - " 3 y s t e m - - 2 2 e g i s t e r s - " $ a t a 3 2 ! - " i t " a n d ! l i a s m a x - " , - a i n 3 2 ! - $ a t a m a x + " - e m 9 3 0 ) 3 - # # o d e 3 p a c e - " , # o d e 3 2 ! - m a x + " , " o o t 2 / - + " ) . 4 % 2 . ! , - % - / 2 9 % 8 4 % 2 . ! , - % - / 2 9 ) . 4 % 2 . ! , - % - / 2 9 x & & & & & & & & x & x % x % x % & & x % x % x # x ! x x x x x x x x x x x x # x x x x ! x x x x x x preliminary technical data rev. prf | page 9 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f arm cortex-m4 memory subsystem the memory map of the adsp-cm40xf family is based on the cortex-m4 model from arm. by retaining the standardized memory mapping, it becomes easier to port applications across m4 platforms. only the physical implementation of memories inside the model differ s from other vendors. adsp-cm40xf application develo pment is typically based on memory blocks across code/sram and external memory regions. sufficient internal memory is available via internal sram and internal flash. additional external memory devices may be interfaced via the smc asynchronous memory port, as well as through the spi0 serial memory interface. code region accesses in this region (0x 0000_0000 to 0x1fff_ffff) are per- formed by the core on its ic ode and dcode interfaces, and they target the memory and cache resources within the cortex-m4f platform integration component. ? boot rom. a 32k byte boot rom executed at system reset. this space supports read -only access by the m4f core only. note that rom memory contents cannot be modified by the user. ? internal sram code region. this memory space con- tains the application instructions and literal (constant) data which must be executed real time. it supports read/write access by the m4f core and read/write dma access by sys- tem devices. internal sram can be partitioned between code and data (sram region in m4 space) in 64k byte blocks. access to this region occurs at core clock speed, with no wait states. ? integrated flash. this contains the 2m byte flash memory space interfaced via the spi2 port of the processor. this memory space contains the application instructions and lit- eral (constant) data. reads from flash memory are directly cached via internal code cache. direct memory-mapped reads are permitted via spi memory-mapped protocol internal flash memory ships fr om the factory in an erased state except for sector 0 of the main flash array. sector 0 of the main flash array ships from the factory in an unknown state. an erase operation shou ld be performed prior to pro- gramming this sector. ? internal code cache. a zero-wait-state code cache sram memory is available internally (not visible in the memory map) to cache instruction access from internal flash as well as any externally connected serial flash and asynchronous memory. ? mem-x/mem-y. these are virtual memory blocks which are used as cacheable memory for the code cache. no phys- ical memory device resides inside these blocks. the application code must be compiled against these memory blocks to utilize the cache. sram region accesses in this region (0x 2000_0000 to 0x3fff_ffff) are per- formed by the arm cortex-m4f co re on its sys interface. the sram region of the core can otherwise act as a data region for an application. ? internal sram data region. this space can contain read/write data. internal sram can be partitioned between code and data (sram region in m4 space) in 64k byte blocks. access to this region occurs at core clock speed, with no wait states. it suppo rts read/write access by the m4f core and read/write dma access by system devices. it supports exclusive memory acce sses via the global exclusive access monitor within the co rtex-m4f platform. bit-band- ing support is also available. system memory spaces ? external spi flash. up to 16m byte of ex ternal serial quad flash memory optionally connec ted to the spi0 port of the processor. reads from flash me mory are directly cached via internal code cache. direct memory-mapped reads are per- mitted via spi memory-mapped protocol. ? system mmrs. various system mmrs reside in this region. bit-banding support is available for mmrs. external asynchronous parallel flash/ram ? l2 asynchronous memory. up to 32m byte 4 banks of external memory can be option ally connected to the asyn- chronous memory port (smc). code execution from these memory blocks can be optionally cached via internal code cache. direct r/w data access is also possible. system region accesses in this region (0xe 000_0000 to 0xf7ff_ffff) are per- formed by the arm cortex-m4f core on its sys interface, and are handled within the cortex-m 4f platform. the mpu may be programmed to limit access to this space to privileged mode only. ? coresight rom. the rom table entries point to the debug components of the processor. ? arm ppb peripherals. this space is defined by arm and occupies the bottom 256k byte of the sys region (0xe000_0000 to 0xe004_0000). the space supports read/write access by the m4f core to the arm cores inter- nal peripherals (mpu, itm, dw t, fpb, scs, tpiu, etm) and the coresight rom. it is not accessible by system dma. ? platform control registers. this space has registers within the cortex-m4f plat form integration component that control the arm core, its memory, and the code cache. it is accessible by the m4f core via its sys port (but is not accessible by system dma). rev. prf | page 10 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data static memory controller (smc) the smc can be programmed to control up to four banks of external memories or memory-ma pped devices, with very flexi- ble timing parameters. on adsp-cm407f/cm408f/cm409f processors, each bank can occu py a 32m byte segment regard- less of the size of the device used. booting the processor has several mechan isms for automatically loading internal and external memory af ter a reset. the boot mode is defined by the sys_bmode input pins dedicated for this pur- pose. there are two categories of boot modes. in master boot modes, the processor actively lo ads data from a serial memory. in slave boot modes, the processo r receives data from external host devices. the boot modes are shown in table 2 . these modes are imple- mented by the sys_bmode bits of the rcu_ctl register and are sampled during power-on re sets and software-initiated resets. system acceleration the following sections describe the system acceleration blocks of the adsp-cm40xf processors. harmonic analysis engine (hae) the harmonic analysis engine (hae) block receives 8 khz input samples from two source signals whose frequencies are between 45 hz and 65 hz. the hae will then process the input samples and produce output result s. the output results consist of power quality measurements of the fundamental and up to 12 additional harmonics. sinc filter the sinc module processes four bit streams using a pair of configurable sinc filters for each bitstream. the purpose of the primary sinc filter of each pair is to produce the filtered and decimated output for the pair. the output may be decimated to any integer rate betw een 8 and 256 times lo wer than the input rate. greater decimation allows greater remova l of noise and therefore greater enob. optional additional filtering outside the sinc module may be used to further increase enob. the primary sinc filter output is accessible through transfer to processor memory, or to another peripheral, via dma. each of the four channels is al so provided with a low-latency secondary filter with programmable positive and negative over- range detection comparators. th ese limit detection events can be used to interrupt the core, generate a trigger, or signal a sys- tem fault. security features the processor provides a combination of hardware and soft- ware protection mechanisms that lock out access to the part in secure mode, but grant access in open mode. these mechanisms include password-protected slave boot modes (spi and uart), as well as password-protected jtag/swd debug interfaces. processor reliability features the processor provides the following features which can enhance or help achieve certain le vels of system safety and reli- ability. while the level of safety is mainly dominated by system considerations, the following feat ures are provided to enhance robustness. multi-parity-bit-protected l1 memories in the processors sram and ca che l1 memory space, each word is protected by multiple parity bits to detect the single event upsets that occur in all rams. cortex mpu the mpu divides the memory map into a number of regions, and allows the system programmer to define the location, size, access permissions, and memory attributes of each region. it supports independent attribute settings for each region, over- lapping regions, and export of me mory attributes to the system. for more information, refer to http://infocenter.arm.com/ system protection all system resources and l2 memo ry banks can be controlled by either the processor core, memory-to-memory dma, or the debug unit. a system protecti on unit (spu) enables write accesses to specific resources th at are locked to a given master. system protection is enabled in greater granularity for some modules through a global lock concept. watchpoint protection the primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. when enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user -defined addre sses. watchdog events can be configured such that they signal the events to the core or to the sec. software watchdog the on-chip watchdog timer can provide software-based super- vision of the adsp-cm40xf core. table 2. boot modes sys_bmode[1:0] setting description 00 no boot/idle. the processor does not boot. rather the boot kernel executes an idle instruction. 01 flash boot. boot from integrated flash memory through the spi2. 10 spi slave boot. boot through the spi0 peripheral configured as a slave. 11 uart boot. boot through the uart0 peripheral configured as a slave. preliminary technical data rev. prf | page 11 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f signal watchdogs the eight general-purp ose timers feature two modes to monitor off-chip signals. the watchdog period mode monitors whether external signals toggle with a peri od within an expected range. the watchdog width mode monito rs whether the pulse widths of external signals are in an expe cted range. both modes help to detect incorrect undesired toggling (or lack thereof) of system-level signals. oscillator watchdog the oscillator watchdog monitors the external clock oscillator, and can detect the absence of clock as well as incorrect har- monic oscillation. the oscillator watchdog detection signal is routed to the fault management portion of the system event controller. low-latency sinc filter over-range detection the sinc filter units provide a lo w-latency secondary filter with programmable positive and negative limit detectors for each input channel. these may be used to monitor an isolation adc bitstream for over- or under-range conditions with a filter group delay as low as 0.7 s on a 10 mhz bitstream. the sec- ondary sinc filter events can be used to interrupt the core, to trigger other events directly in hardware using the trigger rout- ing unit (tru), or to signal the fault management unit of a system fault. up/down count mismatch detection the gp counter can monitor external signal pairs, such as request/grant strobes. if the ed ge count mismatch exceeds the expected range, the up/down counte r can flag this to the proces- sor or to the sec. fault management the fault management unit is part of the system event controller (sec). most system events can be defined as faults. if defined as such, the sec forwards the event to its fault management unit which may automatically reset the entire device for reboot, or simply toggle the sys_fault output pin to signal off-chip hardware. optionally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chance for the core to resolve the crisis and to prevent the fault action from being taken. additional processor peripherals the processor contains a rich set of peripherals connected to the core via several concurrent hi gh-bandwidth buses, providing flexibility in system configurat ion as well as excellent overall system performance (see the block diagram on page 1 ). the processor contains high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power manage- ment control functions to tail or the performance and power characteristics of the processor and system to many application scenarios. the following sections describe additional peripherals that were not described in the previous sections. timers the processor includes several ti mers which are described in the following sections. general-purpose timers the gp timer unit provides ei ght general-purp ose programma- ble timers. each timer has an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be syn- chronized to an external clock input on the tm0_aclkx pins, an external signal on the tm0_clk input pin, or to the internal sclk. the timer unit can be used in conjunction with the uarts and the can controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timer can generate interrupts to the processor core, provid- ing periodic events for synchron ization to either the system clock or to external signals. timer events can also trigger other peripherals via the tru (for in stance, to signal a fault). watchd og timer the core includes a 32-bit timer, which may be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state, via generation of a genera l-purpose interrupt, if the timer expires before being reset by so ftware. the programmer initial- izes the count value of the ti mer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. this protects th e system from remaining in an unknown state where software, wh ich would normally reset the timer, has stopped running due to an external noise condition or software error. optionally , the fault management unit (fmu) can directly initiate the processor reset upon the watch- dog expiry event. 3-phase pwm units the pulse width modulator (pwm) unit provides duty cycle and phase control capabilities to a resolution of one system clock cycle (sclk). the heightened precision pwm (hppwm) module provides in creased performance to the pwm unit by increasing its resolu tion by several bits, resulting in enhanced precision levels. additional features include: ? 16-bit center-based pwm generation unit ? programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ?twos-complement implementa tion which permits smooth transition to full on and full off states ? dedicated asynchronous pwm shutdown signal each pwm block integrates a flexible and programmable 3-phase pwm waveform generator that can be programmed to generate the required switchin g patterns to drive a 3-phase rev. prf | page 12 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data voltage source inverter for ac induction motor (acim) or per- manent magnet synchronous motor (pmsm) control. in addition, the pwm block contains special functions that con- siderably simplify the generation of the required pwm switching patterns for control of the electronica lly commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for swit ched reluctance motors (srm). the eight pwm output signals (p er pwm unit) consist of four high-side drive signals and four low-side drive signals. the polarity of a generated pwm signal can be set with software, so that either active hi or ac tive lo pwm patterns can be produced. each pwm unit features a dedi cated asynchronous shutdown pin which (when brought low) in stantaneously places all pwm outputs in the off state. serial ports (sports) the synchronous serial ports pr ovide an inexpe nsive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices audi o codecs, adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels.for full-duplex operation, two half sports can work in conjunction with clock and frame sync signals shared internally through the spmux block. in some operation modes, sport supports gated clock. serial ports operate in six modes: ? standard dsp serial mode ? multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ?left-justified mode ?right-justified mode general-purpose counters the 32-bit counter can operate in general-purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. count direction is either controlled by a level-sensitive input pin or by two edge detectors. a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins ha ve a programmable debouncing circuit. the gp counter can also support a programmable m/n fre- quency scaling of the cnt_cud and cnt_cdg pins onto output pins in quadrature encoding mode. internal signals forwarded to ea ch general-purpose timer enable these timers to measure the in tervals between count events. boundary registers enable auto-z ero operation or simple system warning by interrupts when pr ogrammable count values are exceeded. serial peripheral interface (spi) ports the processor contains the spi-co mpatible port that allows the processor to communicate with multiple spi-compatible devices. in its simplest mode, the spi inte rface uses three pins for trans- ferring data: two data pins master output-slave input and master input-slave output (spi_mosi and spi_miso) and a clock pin, spi_clk. a spi chip select input pin (spi_ss ) lets other spi devices select the processor, and three spi chip select output pins (spi_seln) let the processor select other spi devices. the spi select pins ar e reconfigured general-purpose i/o pins. using these pins, the spi provides a full-duplex, syn- chronous serial interface, whic h supports both master and slave modes and multimaster environments. in a multi-master or multi-sl ave spi system, the mosi and miso data output pins can be configured to behave as open drain outputs (using the odm bi t) to prevent contention and possible damage to pin drivers. an external pull-up resistor is required on both the mosi and miso pins when this option is selected. when odm is set and the spi is configured as a master, the mosi pin is three-stated when the data driven out on mosi is a logic-high. the mosi pin is not three-stated when the driven data is a logic-low. similarly, when odm is set and the spi is configured as a slave, the miso pin is three-stated if the data driven out on miso is a logic-high. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has integrated dma channels for both transmit and rece ive data streams. uart ports the processor provides full-du plex universal asynchronous receiver/transmitter (uart) ports, which are fully compatible with pc-standard uarts. each uart port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-support ed, asynchronous transfers of serial data. a uart port includes suppo rt for five to eight data bits, and none, even, or odd parity. optionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminated by one, one and a half, two or two and a half stop bits. the uart ports support automa tic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmab le assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. preliminary technical data rev. prf | page 13 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processor includes a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi modu le is compatible with the widely used i 2 c bus standard. the twi module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (twi_scl) and data (twi_sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compati- ble with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. controller area network (can) the can controller implements the can 2.0b (active) proto- col. this protocol is an asynchronous communications protocol used in both industrial and au tomotive contro l systems. the can protocol is well suited for control applications due to its capability to commun icate reliably over a network. this is because the protocol incorporat es crc checking, message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (id) message formats. ? support for remote frames. ? active or passive network support. ? interrupts, including: tx complete, rx complete, error and global. an additional crystal is not required to supply the can clock, as the can clock is derived from a system clock through a pro- grammable divider. 10/100 ethernet mac the processor can directly connec t to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 et hernet mac peripheral on the processor is fully compliant to the ieee 802.3-2002 standard. it provides programmable features designed to minimize supervi- sion, bus use, or message processi ng by the rest of the processor system. some standard features are: ? support for rmii protocols for external phys ? full-duplex and half-duplex modes ? media access management (in half-duplex operation) ? flow control ? station management: generation of mdc/mdio frames for read-write access to phy registers some advanced features are: ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to memory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes ? 47 mac management statistics counters with selectable clear-on-read behavior and pr ogrammable interrupts on half maximum value ? advanced power management ? magic packet detection and wakeup frame filtering ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ieee 1588 support the ieee 1588 standard is a pr ecision clock synchronization protocol for networked measurement and control systems. the processor includes hardware support for ieee 1588 with an integrated precision time protoc ol synchronization engine. this engine provides hard ware assisted time stamping to improve the accuracy of clock synchron ization between ptp nodes. the main features of the engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? 64-bit hardware assi sted time stamping for transmit and receive frames capable of up to 10 ns resolution ? identification of ptp message type, version, and ptp pay- load in frames sent directly over ethernet and transmission of the status ? coarse and fine correction me thods for system time update ? alarm features: target time can be set to interrupt when system time reaches target time ? pulse-per-second output for ph ysical representation of the system time. flexibility to control the pulse-per-second (pps) output signal including control of start time, stop time, pps output width and interval ? automatic detection and time stamping of ptp messages over ipv4, ipv6 and ethernet packets ? multiple input clock sources (sclk, rmii clock, external clock) ? auxiliary snapshot to time stamp external events rev. prf | page 14 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data usb 2.0 on-the-go dual-role device controller the usb 2.0 otg dual-role device controller provides a low- cost connectivity solution for th e growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, di gital still cameras, and mp3 players. the usb 2.0 controller is a full-speed-only (fs) inter- face that allows these devices to transfer data using a point-to- point usb connection without the need for a pc host. the module can operate in a tradit ional usb peripheral-only mode as well as the host mode presented in the on-the-go (otg) supplement to the usb 2.0 specification. clock and power management the processor provides three operating modes, each with a dif- ferent performance/power profile. control of clocking to each of the processor peripherals al so reduces power consumption. see table 3 for a summary of the power settings for each mode. crystal oscillator (sys_xtal) the processor can be clocked by an external crystal ( figure 8 ), a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified fr equency during normal opera- tion. this signal is connecte d to the processors sys_clkin pin. when an external clock is used, the sys_xtal pin must be left unconnected. alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 8 . a parallel-resonant, fund amental frequency, micro- processor grade crystal is conn ected across the sys_clkin and xtal pins. the on-chip resist ance between sys_clkin and the xtal pin is in the 500 k ra nge. further parallel resistors are typically not recommended. the two capacitors and the series resistor shown in figure 8 fine tune phase and amplitude of the sine frequency. the capacitor and resistor va lues shown in figure 8 are typical values only. the capacitor values are depend ent upon the crystal manufac- turers load capacitance recomm endations and the pcb physical layout. the resistor value depends on the drive level specified by the crystal manufacturer. the user should verify the customized values based on careful investigat ions on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in figure 8 . a design procedure for third-overtone operation is discussed in detail in application note ee-168: using third overtone crysta ls with the adsp-218x dsp on the analog devices website ( www.analog.com )use site search on ee-168. oscillator watchdog a programmable oscilla tor watchdog unit is provided to allow verification of proper startup and harmonic mode of the exter- nal crystal. this allows the user to specify the expected frequency of oscillation, and to enable detection of non-oscilla- tion and improper-oscillation faults. these events can be routed to the sys_fault output pin and/or to cause a reset of the part. clock generation the clock generation unit (cgu ) generates all on-chip clocks and synchronization signals. mu ltiplication factors are pro- grammed to the plls to define the pllclk frequency. programmable values divide the pllclk frequency to generate the core clock (cclk), the system clocks (sclk) and the out- put clock (oclk). this is illustrated in figure 10 on page 61 . writing to the cgu control registers does not affect the behav- ior of the pll immediately. regi sters are first programmed with a new value, and the pll logic executes the changes so that it transitions smoothly from the current conditions to the new ones. sys_clkin oscillations start when power is applied to the v dd_ext pins. the rising edge of sys_hwrst can be applied as soon as all voltage supplies are within specifications (see oper- ating conditions on page 61 ), and sys_clkin oscillations are stable. table 3. power settings mode cgu pll cgu pll bypassed f cclk f sclk core power full on enabled no enabled enabled on active enabled yes enabled enabled on disabled yes enabled enabled on deep sleep disabled disabled disabled on figure 8. external crystal connection sys_clkin to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18pf should be treated as a maximum, and the suggested 5 ( 6 , 6 7 2 5 9 $ / 8 ( 6 + 2 8 / ' % ( 5 ( ' 8 & ( ' 7 2 18 pf* 18 pf * * adsp-cm40xf sys_xtal preliminary technical data rev. prf | page 15 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f clock out/external clock a sys_clkout output pin has programmable options to out- put divided-down versions of the on-chip clocks, including usb clocks. by default, the sys_cl kout pin drives a buffered ver- sion of the sys_clkin input. clock generation faults (for example pll unlock) may tri gger a reset by hardware. sys_clkout can be used to ou tput one of several different clocks used on the processor. the clocks shown in table 4 can be outputs from sys_clkout. power management as shown in table 5 and figure 4 on page 5 , the processor sup- ports three different power domains, v dd_int , v dd_ext and v dd_ana . by isolating the internal logic of the processor into its own power domain, separate from other i/o, the processor can take advantage of dynamic power management without affect- ing the other i/o devices. there are no sequencing requirements for the various power domains, but all domains must be powered accord ing to the appropriate specifications table for processor operating conditions; even if the fea- ture/peripheral is not used. the dynamic power management feature of the processor allows the processors core clock frequency (f cclk ) to be dynam- ically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation. for more information on power pins, see operating conditions on page 61 . full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the execution state in which maximum performance can be achieved. the processor core and all enabled peripherals run at full speed. for more information about pl l controls, see the dynamic power management chapter in the adsp-cm40xf mixed-sig- nal control processor with arm cortex-m4 and 16-bit adcs hardware reference . deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proce ssor core and to all synchronous peripherals. asynchronous periph erals may still be running but cannot access internal reso urces or external memory. voltage regulation for vdd_int the internal voltage v dd_int to the adsp-cm40xf processors can be generated either by using an on-chip voltage regulator or by an external voltage regulator. the v dd_int of 1.2 v can be generated using the external i/o supply v dd_vreg of 3.3 v, which is then used to generate v dd_int of 1.2 v. figure 9 shows the external components required to complete the power management system for proper operation. for more details regarding compon ent selection, please refer to ee-361: adsp-cm40x power su pply transistor selection guidelines . the internal voltage regulator can be bypassed and v dd_int can be supplied using an external re gulator. when an external regu- lator is used, v dd_vreg and v reg_base must be tied to ground for zero current consumption. reset control unit reset is the initial state of the wh ole processor or of the core and is the result of a hardware or software triggered event. in this state, all control regist ers are set to their default values and func- tional units are idle. exiting a core only reset starts with the core being ready to boot. the reset control unit (rcu) co ntrols how all the functional units enter and exit reset. differences in functional require- ments and clocking constraints define how reset signals are generated. programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. from a system perspective reset is defined by both the reset tar- get and the reset source as described below. table 4. sys_clkout source and divider options clock source divider cclk (core clock) by 4 oclk (output clock) programmable usbclk programmable clkbuf none, direct from sys_clkin table 5. power domains power domain pin all internal logic v dd_int digital i/o v dd_ext analog v dd_ana figure 9. internal voltage regulator circuit v dd_vreg std2805t4 1k v reg_base v dd_int 3.3v 10 - 220f 0.1f rev. prf | page 16 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data target defined: ? hardware reset C all functional units are set to their default states without exception. history is lost. ? system reset C all functional units except the rcu are set to their default states. source defined: ? hardware reset C the sys_hwrst input signal is asserted active (pulled down). ? system reset C may be triggered by software (writing to the rcu_ctl register) or by another functional unit such as the dynamic power management (dpm) unit or any of the system event controller (sec), trigger routing unit (tru), or emulator inputs. ? trigger request (peripheral). system debug the processor includes various fe atures that allow for easy sys- tem debug. these are described in the following sections. jtag debug and serial wire debug port (swj-dp) swj-dp is a combined jtag -dp and sw-dp that enables either a serial wire debug (s wd) or jtag probe to be con- nected to a target. swd signals share the same pins as jtag. there is an auto detect mech anism that switches between jtag-dp and sw-dp depending on which special data sequence is used the emulator pod transmits to the jtag pins.the swj-dp behaves as a jtag target if normal jtag sequences are sent to it and as a single wire target if the sw_dp sequence is transmitted. embedded trace macrocell (etm) and instrumentation trace macrocell (itm) the adsp-cm40xf processors su pport both embedded trace macrocell (etm) and instrumentation trace macrocell (itm). these both offer an optional de bug component that enables log- ging of real-time instruction and data flow within the cpu core. this data is stored and read through special debugger pods that have the trace feature capability . the itm is a single-data pin feature and the etm is a 4-data pin feature. system watchpoint unit the system watchpoint unit (s wu) is a single module which connects to a single system bu s and provides for transaction monitoring. one swu is attached to the bus going to each system slave. the swu provides ports for all syst em bus address channel signals. each swu contains four match groups of registers with associated ha rdware. these four swu match groups operate independently, but share common event (inter- rupt and trigger) outputs. development tools the adsp-cm40xf processor is su pported with a set of highly sophisticated and easy-to-use de velopment tools for embedded applications. for more information, see the analog devices website. additional information the following publications that describe the adsp- cm402f/cm403f/cm407f/cm408f/c m409f processors (and related processors) can be orde red from any analog devices sales office or accessed electronically on our website: ? adsp-cm40xf mixed-signal control processor with arm cortex-m4 and 16-bit ad cs hardware reference ? adsp-cm40xf mixed-signal control processor with arm cortex-m4 and 16-bit adcs anomaly list this document describes the arm cortex-m4 core and mem- ory architecture used on the adsp-cm40xf processor, but does not provide detailed programming information for the arm processor. for more informat ion about programming the arm processor, visit the arm information center at: http://infocenter.arm.com/help/ the applicable documentation for programming the arm cor- tex-m4 processor include: ?cortex ? -m4 devices generic user guide ?coresight tm etm tm -m4 technical reference manual ?cortex ? -m4 technical reference manual related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog.com/circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques preliminary technical data rev. prf | page 17 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm40xf detailed signal descriptions table 6 provides a detailed description of each pin. table 6. adsp-cm40xf detailed signal description signal name direction description adc_vinnn input channel nn single-ended analog input for adcs. nn = 00 to 11 for each adc byp_an on-chip analog power regulation bypass filter node for adc. connect to decoupling capacitors. n = 0, 1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem. connect to decoupling capacitors. can_rx input can receive typically an external can transceivers rx output. can_tx output can transmit typically an external can transceivers tx input. cnt_outa output counter output divider a frequency scaled output in quadrature encoder mode of gp counter cnt_outb output counter output divider b frequency scaled output in quadrature encoder mode of gp counter cnt_dg input cnt count down and gate depending on the mode of operation this input acts either as a count down signal or a gate signal. count down: this input causes the gp counter to decrement. gate: stops the gp counter from incrementing or decrementing. cnt_ud input count up and direction depending on the mode of operation this input acts either as a count up signal or a direction signal. count up: this input causes the gp counter to increment. direction: selects whether the gp counter is incrementing or decrementing. cnt_zm input count zero marker input that connects to the zero marker output of a rotary device or detects the pressing of a push button. cptmr_inn input capture timer input pins n = 0, 1, 2 dacn_vout output dac output analog voltage output. n = 0, 1 eth_crs input emac carrier sense multiplexed on alternate clock cycles. crs: asserted by the phy when either the transmit or receive medium is not idle. de-asserted when both are idle. rxdv: asserted by the phy when the data on rxdn is valid. eth_mdc output emac management channel clock clocks the mdc input of the phy. eth_mdio i/o emac management channel serial data bidirectional data bus for phy control. eth_ptpauxin input emac ptp auxiliary trigger input assert this signal to take an auxiliary snapshot of the time and store it in the auxiliary time stamp fifo. eth_ptpclkin input emac ptp clock input optional external ptp clock input. eth_ptppps output emac ptp pulse-per-second output when the advanced time stamp feature is enabled, this signal is asserted based on the pps mode selected. otherwise, pt ppps is asserted every time the seconds counter is incremented. eth_refclk input emac reference clock externally supplied ethernet clock. eth_rxdn input emac receive data n receive data bus. n = 0, 1 eth_txdn output emac transmit data n transmit data bus. n = 0, 1 eth_txen i/o emac transmit enable when asserted indicates that the data on txdn is valid. jtg_swclk i/o serial wire clock clocks data into and out of the target during debug. jtg_swdio i/o serial wire data io sends and receives serial data to and from the target during debug. jtg_swo output serial wire out provides trace data to the emulator. jtg_tck input jtag clock jtag test access port clock. jtg_tdi input jtag serial data in jtag test access port data input. jtg_tdo output jtag serial data out jtag test access port data output. jtg_tms input jtag mode select jtag test access port mode select. rev. prf | page 18 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data jtg_trst input jtag reset jtag test access port reset. px_nn i/o position n general purpose input/output. see the gp ports chapter in the processor hardware reference for programming information. pwm_ah output pwm channel a high side high side drive signal. pwm_al output pwm channel a low side low side drive signal. pwm_bh output pwm channel b high side high side drive signal. pwm_bl output pwm channel b low side low side drive signal. pwm_ch output pwm channel c high side high side drive signal. pwm_cl output pwm channel c low side low side drive signal. pwm_dh output pwm channel d high side high side drive signal. pwm_dl output pwm channel d low side low side drive signal. pwm_sync i/o pwm synchronization signal this is an input pin when pwm is configured to receive external sync signal. it is an output pin when pwm sync is generated internally. pwm_tripn input pwm shutdown input when asserted the selected pwm cha nnel outputs are shut down immediately. refcap analog output of bandg ap generator filter node sinc_clkn output sinc clock n n = 0, 1 sinc_dn input sinc data n n = 0 to 3 smc_ann output smc address n address bus. n = 0 to 24 smc_aben output smc byte enable n indicates whether the lower or upper byte of a memory is being accessed. when an asynchronous write is made to the upper byte of a 16-bit memory, smc_abe1 = 0 and smc_abe0 = 1. when an asynchronous write is made to the lower b yte of a 16-bit memory, smc_abe1 = 1 and smc_abe0 = 0. smc_amsn output smc memory select n typically connects to the chip select of a memory device. n = 0, 1, 2, 3 smc_aoe output smc output enable asserts at the beginning of the setup period of a read access. smc_ardy input smc asynchronous ready flow control signal used by memory devi ces to indicate to the smc when further transactions may proceed. smc_are output smc read enable asserts at the beginning of a read access. smc_awe output smc write enable asserts for the duration of a write access period. smc_dnn i/o smc data n bidirectional data bus. n = 0 to 15 spi_clk i/o spi clock input in slave mode, output in master mode. spi_d2 i/o spi data 2 used to transfer serial data in quad mode. open drain in odm mode. spi_d3 i/o spi data 3 used to transfer serial data in quad mode. open drain in odm mode. spi_miso i/o spi master in, slave out used to transfer serial data. operates in the same direction as spi_mosi in dual and quad modes. open drain in odm mode. spi_mosi i/o spi master out, slave in used to transfer serial data. operates in the same direction as spi_miso in dual and quad modes. open drain in odm mode. spi_rdy i/o spi ready optional flow signal to hold-off faster master s. output in slave mode, input in master mode. spi_seln output spi slave select output n used in master mode to enable the desired slave. spi_ss input spi slave select input slave mode: acts as the slave select input. master mode: optionally serves as an error detection input for the spi when there are multiple masters. spt_aclk i/o sport a channel clock data and frame sync are driven/sampled with respect to this clock. this signal can be either internally or externally generated. spt_ad0 i/o sport a channel data 0 primar y bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_ad1 i/o sport a channel data 1 secondary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. table 6. adsp-cm40xf detailed signal description (continued) signal name direction description preliminary technical data rev. prf | page 19 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f spt_afs i/o sport a channel frame sync the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. spt_atdv output sport a channel transmit data valid this signal is optional and only active when sport is configured in multi-channel transmit mode. it is asserted during enabled slots. spt_bclk i/o sport b channel clock data and frame sync are driven/sampled with respect to this clock. this signal can be either internally or externally generated. spt_bd0 i/o sport b channel data 0 primary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_bd1 i/o sport b channel data 1 secondary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_bfs i/o sport b channel frame sync the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. spt_btdv output sport b channel transmit data valid this signal is optional and only active when sport is configured in multi-channel transmit mode. it is asserted during enabled slots. sys_bmoden input boot mode control n selects the boot mode of the processor. n = 0, 1 sys_clkin input processor clock/crystal input connect to an external clock source or crystal. sys_clkout output processor clock output outputs internal clocks. clocks may be divided down. see the cgu chapter in the processor hardware refe rence for more details. sys_dswaken input system deep sleep wakeup inputs . n = 0 to 3 sys_fault output complementary fault indicates system fault. sys_hwrst input processor hardware reset control resets the device when asserted. sys_nmi input non-maskable interrupt see the processor hardware and programming references for more details. sys_resout output processor reset output indicates that the device is in the reset state. sys_xtal output system crystal output drives an external crystal. must be left unconnected if an external clock is driving clkin. tm_acin input gp timer alternate capture input n provides an additional input for gp timers in widcap, watchdog, and pinint modes. n = 0 to 5 tm_aclkn input gp timer alternate clock n provides an additional time base for use by an individual timer. n = 0 to 5 tm_clk input gp timer clock provides an additional global time base for use by all the gp timers. tm_tmrn i/o gp timer timer n the main input/output signal for each timer. n = 0 to 7. in pwm out mode, output is driven on this pin. in width capture mode, it acts as input an d timer measures width and/or period of incoming signal on this pin. in extclk mode, timer counts number of incoming signal edges on this pin. trace_clk output embedded trace module clock reference clock for the trace unit. trace_dn output embedded trace module data n output data for clocked modes and changes on both edges of trace_clk. n = 0 to 3 twi_scl i/o twi serial clock clock output when master, clock input when slave. compatible with i 2 c bus standard. twi_sda i/o twi serial data receives or transmits data. compatible with i 2 c bus standard. uart_cts input uart clear to send input hardware flow control signal. transmitter initiates the transfer only when this signal is active. uart_rts output uart request to send output hardware flow control signal. receiver activates this signal when it is ready to receive new transfers. uart_rx input uart receive receive input. typically connects to a transceiver that meets the electrical requirements of the device being communicated with. uart_tx output uart transmit transmit output. typically connects to a transceiver that meets the electrical requirements of the device being communicated with. usb_dm i/o usb data C bidirectional differential data line. usb_dp i/o usb data + bidirectional differential data line. table 6. adsp-cm40xf detailed signal description (continued) signal name direction description rev. prf | page 20 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data usb_id input usb otg id senses whether the controller is a host or device. this signal is pulled low when an a-type plug is sensed (signifying that the usb controller is the a device ), but the input is high when a b-type plug is sensed (signifying that the usb controller is the b device). usb_vbc output usb vbus control controls an external voltage source to supply vbus when in host mode. may be configured as open drain. polarity is configurable as well. usb_vbus i/o usb bus voltage connects to bus voltage in host and device modes. vrefn i/0 voltage reference for adc when internal reference is selected for adc, the vref pin is used for connecting bypass caps. when external reference is selected, this pin is used to feed external reference voltage. vreg_base output voltage regulator base node connected to base of pnp transistor when using internal vddint reference. table 6. adsp-cm40xf detailed signal description (continued) signal name direction description preliminary technical data rev. prf | page 21 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm402f/adsp-cm403f 120-le ad lqfp signal descriptions the processors pin de finitions are shown table 7 . the columns in this table provide the following information: ? signal name - the signal name column in the table includes the signal name for every pin an d (where applica- ble) the gp i/o multiplexed pin function for every pin. ? description and notes - the description column in the table provides a verbose (descriptive) name for the signal. ?port - the general-purpose i/o port column in the table whether or not the signal is multiplexed with other signals on a general-purpose i/o port pin. ? pin name - the pin name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multi- plexed (if a general-purpose i/o pin). table 7. adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions signal name description port pin name adc0_vin00 channel 0 single -ended analog input for adc0 not muxed adc0_vin00 adc0_vin01 channel 1 single -ended analog input for adc0 not muxed adc0_vin01 adc0_vin02 channel 2 single -ended analog input for adc0 not muxed adc0_vin02 adc0_vin03 channel 3 single -ended analog input for adc0 not muxed adc0_vin03 adc0_vin04 channel 4 single -ended analog input for adc0 not muxed adc0_vin04 adc0_vin05 channel 5 single -ended analog input for adc0 not muxed adc0_vin05 adc0_vin06 channel 6 single -ended analog input for adc0 not muxed adc0_vin06 adc0_vin07 channel 7 single -ended analog input for adc0 not muxed adc0_vin07 adc0_vin08 channel 8 single -ended analog input for adc0 not muxed adc0_vin08 adc0_vin09 channel 9 single -ended analog input for adc0 not muxed adc0_vin09 adc0_vin10 channel 10 sing le-ended analog input for adc0 not muxed adc0_vin10 adc0_vin11 channel 11 sing le-ended analog input for adc0 not muxed adc0_vin11 adc1_vin00 channel 0 single -ended analog input for adc1 not muxed adc1_vin00 adc1_vin01 channel 1 single -ended analog input for adc1 not muxed adc1_vin01 adc1_vin02 channel 2 single -ended analog input for adc1 not muxed adc1_vin02 adc1_vin03 channel 3 single -ended analog input for adc1 not muxed adc1_vin03 adc1_vin04 channel 4 single -ended analog input for adc1 not muxed adc1_vin04 adc1_vin05 channel 5 single -ended analog input for adc1 not muxed adc1_vin05 adc1_vin06 channel 6 single -ended analog input for adc1 not muxed adc1_vin06 adc1_vin07 channel 7 single -ended analog input for adc1 not muxed adc1_vin07 adc1_vin08 channel 8 single -ended analog input for adc1 not muxed adc1_vin08 adc1_vin09 channel 9 single -ended analog input for adc1 not muxed adc1_vin09 adc1_vin10 channel 10 sing le-ended analog input for adc1 not muxed adc1_vin10 adc1_vin11 channel 11 sing le-ended analog input for adc1 not muxed adc1_vin11 byp_a0 on-chip analog power regulation bypass filter node for adc0 (see recommended bypass - figure 4 ) not muxed byp_a0 byp_a1 on-chip analog power regulation bypass filter node for adc1 (see recommended bypass - figure 4 ) not muxed byp_a1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem (see recommended bypass - figure 4 ) not muxed byp_d0 can0_rx can0 receive b pb_15 can0_tx can0 transmit c pc_00 can1_rx can1 receive b pb_10 can1_tx can1 transmit b pb_11 cnt0_dg cnt0 count down and gate b pb_02 cnt0_outa cnt0 output divider a b pb_13 rev. prf | page 22 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data cnt0_outb cnt0 output divider b b pb_14 cnt0_ud cnt0 count up and direction b pb_01 cnt0_zm cnt0 count zero marker b pb_00 cnt1_dg cnt1 count down and gate b pb_05 cnt1_ud cnt1 count up and direction b pb_04 cnt1_zm cnt1 count zero marker b pb_03 cptmr0_in0 cptmr0 capture timer0 input 0 b pb_07 cptmr0_in1 cptmr0 capture timer0 input 1 b pb_08 cptmr0_in2 cptmr0 capture timer0 input 2 b pb_09 dac0_vout analog voltage output 0 not muxed dac0_vout dac1_vout analog voltage output 1 not muxed dac1_vout gnd digital ground not muxed gnd gnd_ana0 analog ground return for vdd_ana0 (see recommended bypass - figure 4 ) not muxed gnd_ana0 gnd_ana1 analog ground return for vdd_ana1 (see recommended bypass - figure 4 ) not muxed gnd_ana1 gnd_ana2 analog ground (see recommended bypass - figure 4 ) not muxed gnd_ana2 gnd_ana3 analog ground (see recommended bypass - figure 4 ) not muxed gnd_ana3 gnd_vref0 ground return for vref0 (see recommended bypass filter- figure 4 ) not muxed gnd_vref0 gnd_vref1 ground return for vref1 (see recommended bypass filter- figure 4 ) not muxed gnd_vref1 jtg_tck/swclk jtg clock/serial wi re clock not muxed jtg_tck/swclk jtg_tdi jtg serial data in not muxed jtg_tdi jtg_tdo/swo jtg serial data out/serial wire trace output not muxed jtg_tdo/swo jtg_tms/swdio jtg mode select/serial wire debug data i/o not muxed jtg_tms/swdio jtg_trst jtg reset not muxed jtg_trst pa_00-pa_15 port a positions 0 C 15 a pa_00 C pa_15 pb_00-pb_15 port b positions 0 C 15 b pb_00 C pb_15 pc_00-pc_07 port c positions 0 C 7 c pc_00 C pc_07 pwm0_ah pwm0 channel a high side a pa_02 pwm0_al pwm0 channel a low side a pa_03 pwm0_bh pwm0 channel b high side a pa_04 pwm0_bl pwm0 channel b low side a pa_05 pwm0_ch pwm0 channel c high side a pa_06 pwm0_cl pwm0 channel c low side a pa_07 pwm0_dh pwm0 channel d high side b pb_00 pwm0_dl pwm0 channel d low side b pb_01 pwm0_sync pwm0 sync a pa_00 pwm0_trip0 pwm0 shutdown input 0 a pa_01 pwm1_ah pwm1 channel a high side a pa_12 pwm1_al pwm1 channel a low side a pa_13 pwm1_bh pwm1 channel b high side a pa_14 pwm1_bl pwm1 channel b low side a pa_15 pwm1_ch pwm1 channel c high side a pa_08 pwm1_cl pwm1 channel c low side a pa_09 pwm1_dh pwm1 channel d high side b pb_02 pwm1_dl pwm1 channel d low side b pb_03 pwm1_sync pwm1 sync a pa_10 table 7. adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 23 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pwm1_trip0 pwm1 shutdown input 0 a pa_11 pwm2_ah pwm2 channel a high side b pb_06 pwm2_al pwm2 channel a low side b pb_07 pwm2_bh pwm2 channel b high side b pb_08 pwm2_bl pwm2 channel b low side b pb_09 pwm2_ch pwm2 channel c high side c pc_03 pwm2_cl pwm2 channel c low side c pc_04 pwm2_dh pwm2 channel d high side c pc_05 pwm2_dl pwm2 channel d low side c pc_06 pwm2_sync pwm2 sync b pb_04 pwm2_trip0 pwm2 shutdown input 0 b pb_05 refcap output of bandgap generator filter node (see recommended bypass filter - figure 4 ) not muxed refcap sinc0_clk0 sinc0 clock 0 b pb_10 sinc0_clk1 sinc0 clock 1 c pc_07 sinc0_d0 sinc0 data 0 b pb_11 sinc0_d1 sinc0 data 1 b pb_12 sinc0_d2 sinc0 data 2 b pb_13 sinc0_d3 sinc0 data 3 b pb_14 smc0_a01 smc0 address 1 b pb_13 smc0_a02 smc0 address 2 b pb_14 smc0_a03 smc0 address 3 b pb_15 smc0_a04 smc0 address 4 c pc_00 smc0_a05 smc0 address 5 c pc_01 smc0_ams0 smc0 memory select 0 b pb_11 smc0_ams2 smc0 memory select 2 a pa_07 smc0_aoe smc0 output enable b pb_12 smc0_ardy smc0 asynchronous ready b pb_08 smc0_are smc0 read enable b pb_09 smc0_awe smc0 write enable b pb_10 smc0_d00 smc0 data 0 a pa_08 smc0_d01 smc0 data 1 a pa_09 smc0_d02 smc0 data 2 a pa_10 smc0_d03 smc0 data 3 a pa_11 smc0_d04 smc0 data 4 a pa_12 smc0_d05 smc0 data 5 a pa_13 smc0_d06 smc0 data 6 a pa_14 smc0_d07 smc0 data 7 a pa_15 smc0_d08 smc0 data 8 b pb_00 smc0_d09 smc0 data 9 b pb_01 smc0_d10 smc0 data 10 b pb_02 smc0_d11 smc0 data 11 b pb_03 smc0_d12 smc0 data 12 b pb_04 smc0_d13 smc0 data 13 b pb_05 smc0_d14 smc0 data 14 b pb_06 smc0_d15 smc0 data 15 b pb_07 table 7. adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions (continued) signal name description port pin name rev. prf | page 24 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data spi0_clk spi0 clock c pc_03 spi0_d2 spi0 data 2 b pb_10 spi0_d3 spi0 data 3 b pb_11 spi0_miso spi0 master in, slave out c pc_04 spi0_mosi spi0 master out, slave in c pc_05 spi0_rdy spi0 ready c pc_02 spi0_sel1 spi0 slave select output 1 c pc_06 spi0_sel2 spi0 slave select output 2 b pb_13 spi0_sel3 spi0 slave select output 3 b pb_14 spi0_ss spi0 slave select input b pb_14 spi1_sel2 spi1 slave select output 2 b pb_06 spi1_sel3 spi1 slave select output 3 b pb_07 spt0_aclk sport0 channel a clock b pb_00 spt0_ad0 sport0 channel a data 0 b pb_02 spt0_ad1 sport0 channel a data 1 b pb_03 spt0_afs sport0 channe l a frame sync b pb_01 spt0_atdv sport0 channel a transmit data valid b pb_04 spt0_btdv sport0 channel b transmit data valid b pb_12 spt1_aclk sport1 channel a clock a pa_00 spt1_ad0 sport1 channel a data 0 a pa_02 spt1_ad1 sport1 channel a data 1 a pa_03 spt1_afs sport1 channel a frame sync a pa_01 spt1_atdv sport1 channel a transmit data valid b pb_15 spt1_bclk sport1 channel b clock a pa_04 spt1_bd0 sport1 channel b data 0 a pa_06 spt1_bd1 sport1 channel b data 1 a pa_07 spt1_bfs sport1 channel b frame sync a pa_05 spt1_btdv sport1 channel b transmit data valid c pc_00 sys_bmode0 boot mode control 0 not muxed sys_bmode0 sys_bmode1 boot mode control 1 not muxed sys_bmode1 sys_clkin clock/crystal input not muxed sys_clkin sys_clkout processor clock output not muxed sys_clkout sys_dswake0 deep sleep wakeup 0 c pc_06 sys_dswake1 deep sleep wakeup 1 c pc_07 sys_dswake2 deep sleep wakeup 2 b pb_14 sys_dswake3 deep sleep wakeup 3 b pb_13 sys_fault complementary fault output not muxed sys_fault sys_hwrst processor hardware reset control not muxed sys_hwrst sys_nmi non-maskable interrupt not muxed sys_nmi sys_resout reset output not muxed sys_resout sys_xtal crystal output not muxed sys_xtal tm0_aci1 timer0 alternate capture input 1 b pb_10 tm0_aci2 timer0 alternate capture input 2 b pb_08 tm0_aci3 timer0 alternate capture input 3 b pb_12 tm0_aci4 timer0 alternate capture input 4 b pb_15 tm0_aci5 timer0 alternate capture input 5 c pc_01 table 7. adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 25 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f tm0_aclk0 timer0 alternate clock 0 b pb_13 tm0_aclk1 timer0 alternate clock 1 b pb_11 tm0_aclk2 timer0 alternate clock 2 a pa_11 tm0_aclk3 timer0 alternate clock 3 a pa_10 tm0_aclk4 timer0 alternate clock 4 a pa_09 tm0_aclk5 timer0 alternate clock 5 a pa_08 tm0_clk timer0 clock b pb_06 tm0_tmr0 timer0 timer 0 b pb_07 tm0_tmr1 timer0 timer 1 b pb_08 tm0_tmr2 timer0 timer 2 b pb_09 tm0_tmr3 timer0 timer 3 a pa_15 tm0_tmr4 timer0 timer 4 a pa_12 tm0_tmr5 timer0 timer 5 a pa_13 tm0_tmr6 timer0 timer 6 a pa_14 tm0_tmr7 timer0 timer 7 b pb_05 trace_clk embedded trace module clock b pb_00 trace_d00 embedded trace module data 0 b pb_01 trace_d01 embedded trace module data 1 b pb_02 trace_d02 embedded trace module data 2 b pb_03 trace_d03 embedded trace module data 3 c pc_02 twi0_scl twi0 serial clock not muxed twi0_scl twi0_sda twi0 serial data not muxed twi0_sda uart0_cts uart0 clear to send b pb_05 uart0_rts uart0 request to send b pb_04 uart0_rx uart0 receive c pc_01 uart0_tx uart0 transmit c pc_02 uart1_cts uart1 clear to send a pa_11 uart1_rts uart1 request to send c pc_07 uart1_rx uart1 receive b pb_08 uart1_rx uart1 receive b pb_15 uart1_tx uart1 transmit b pb_09 uart1_tx uart1 transmit c pc_00 uart2_rx uart2 receive b pb_12 uart2_tx uart2 transmit c pc_07 vdd_ana0 analog power supply voltage 3.0v to 3.6v (see recommended bypass - figure 4 ) not muxed vdd_ana0 vdd_ana1 analog power supply voltage 3.0v to 3.6v. (see recommended bypass - figure 4 ) not muxed vdd_ana1 vdd_ext external voltage domain not muxed vdd_ext vdd_int internal voltage domain not muxed vdd_int vdd_vreg vreg supply voltage not muxed vdd_vreg vref0 voltage reference for adc0. default configuration is output (see recommended bypass - figure 4 ) not muxed vref0 vref1 voltage reference for adc1. default configuration is output (see recommended bypass - figure 4 ) not muxed vref1 vreg_base voltage regulator base node not muxed vreg_base table 7. adsp-cm402f/adsp-cm403f 120-lead lqfp signal descriptions (continued) signal name description port pin name rev. prf | page 26 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adsp-cm402f/adsp-cm403f general- purpose i/o multiplexing for 120-lead lqfp table 8 through table 10 identify the pin functions that are multiplexed on the general-purp ose i/o pins of the 120-lead lqfp package. table 8. signal multiplexing for port a (120-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pa_00 pwm0_sync spt1_aclk pa_01 pwm0_trip0 spt1_afs pa_02 pwm0_ah spt1_ad0 pa_03 pwm0_al spt1_ad1 pa_04 pwm0_bh spt1_bclk pa_05 pwm0_bl spt1_bfs pa_06 pwm0_ch spt1_bd0 pa_07 pwm0_cl smc0_ams2 spt1_bd1 pa_08 pwm1_ch smc0_d00 tm0_aclk5 pa_09 pwm1_cl smc0_d01 tm0_aclk4 pa_10 pwm1_sync smc0_d02 tm0_aclk3 pa_11 pwm1_trip0 uart1_cts smc0_d03 tm0_aclk2 pa_12 pwm1_ah tm0_tmr4 smc0_d04 pa_13 pwm1_al tm0_tmr5 smc0_d05 pa_14 pwm1_bh tm0_tmr6 smc0_d06 pa_15 pwm1_bl tm0_tmr3 smc0_d07 table 9. signal multiplexing for port b (120-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pb_00 pwm0_dh trace_clk spt0_aclk smc0_d08 cnt0_zm pb_01 pwm0_dl trace_d00 spt0_afs smc0_d09 cnt0_ud pb_02 pwm1_dh trace_d01 spt0_ad0 smc0_d10 cnt0_dg pb_03 pwm1_dl trace_d02 spt0_ad1 smc0_d11 cnt1_zm pb_04 pwm2_sync uart0_rts spt0_atdv smc0_d12 cnt1_ud pb_05 pwm2_trip0 uart0_cts tm0_tmr7 smc0_d13 cnt1_dg pb_06 pwm2_ah tm0_clk spi1_sel2 smc0_d14 pb_07 pwm2_al tm0_tmr0 spi1_sel3 smc0_d15 cptmr0_in0 pb_08 pwm2_bh tm0_tmr1 uart1_rx smc0_ardy tm0_aci2/ cptmr0_in1 pb_09 pwm2_bl tm0_tmr2 uart1_tx smc0_are cptmr0_in2 pb_10 sinc0_clk0 spi0_d2 can1_rx smc0_awe tm0_aci1 pb_11 sinc0_d0 spi0_d3 can1_tx smc0_ams0 tm0_aclk1 pb_12 sinc0_d1 spt0_btdv uart2_rx smc0_aoe tm0_aci3 preliminary technical data rev. prf | page 27 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pb_13 sinc0_d2 cnt0_outa spi0_sel2 smc0_a01 tm0_aclk0/ sys_dswake3 pb_14 sinc0_d3 cnt0_outb spi0_sel3 smc0_a02 spi0_ss / sys_dswake2 pb_15 can0_rx spt1_atdv uart1_rx smc0_a03 tm0_aci4 table 9. signal multiplexing for port b (120-lead lqfp) (continued) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap table 10. signal multiplexing for port c (120-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pc_00 can0_tx spt1_btdv uart1_tx smc0_a04 pc_01 uart0_rx smc0_a05 tm0_aci5 pc_02 uart0_tx trace_d03 spi0_rdy pc_03 spi0_clk pwm2_ch pc_04 spi0_miso pwm2_cl pc_05 spi0_mosi pwm2_dh pc_06 spi0_sel1 pwm2_dl sys_dswake0 pc_07 sinc0_clk1 uart2_tx uart1_rts sys_dswake1 rev. prf | page 28 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adsp-cm407f/ADSP-CM408F 176-le ad lqfp signal descriptions the processors pin definitions are shown table 11 . the col- umns in this table provide the following information: ? signal name - the signal name column in the table includes the signal name for every pin an d (where applica- ble) the gp i/o multiplexed pin function for every pin. ? description and notes - the description column in the table provides a verbose (descriptive) name for the signal. ?port - the general-purpose i/o port column in the table whether or not the signal is multiplexed with other signals on a general-purpose i/o port pin. ? pin name - the pin name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multi- plexed (if a general-purpose i/o pin). table 11. adsp-cm407f/ADSP-CM408F 176- lead lqfp signal descriptions signal name description port pin name adc0_vin00 channel 0 single -ended analog input for adc0 not muxed adc0_vin00 adc0_vin01 channel 1 single -ended analog input for adc0 not muxed adc0_vin01 adc0_vin02 channel 2 single -ended analog input for adc0 not muxed adc0_vin02 adc0_vin03 channel 3 single -ended analog input for adc0 not muxed adc0_vin03 adc0_vin04 channel 4 single -ended analog input for adc0 not muxed adc0_vin04 adc0_vin05 channel 5 single -ended analog input for adc0 not muxed adc0_vin05 adc0_vin06 channel 6 single -ended analog input for adc0 not muxed adc0_vin06 adc0_vin07 channel 7 single -ended analog input for adc0 not muxed adc0_vin07 adc1_vin00 channel 0 single -ended analog input for adc1 not muxed adc1_vin00 adc1_vin01 channel 1 single -ended analog input for adc1 not muxed adc1_vin01 adc1_vin02 channel 2 single -ended analog input for adc1 not muxed adc1_vin02 adc1_vin03 channel 3 single -ended analog input for adc1 not muxed adc1_vin03 adc1_vin04 channel 4 single -ended analog input for adc1 not muxed adc1_vin04 adc1_vin05 channel 5 single -ended analog input for adc1 not muxed adc1_vin05 adc1_vin06 channel 6 single -ended analog input for adc1 not muxed adc1_vin06 adc1_vin07 channel 7 single -ended analog input for adc1 not muxed adc1_vin07 byp_a0 on-chip analog power regulation bypass filter node for adc0 (see recommended bypass - figure 4 ) not muxed byp_a0 byp_a1 on-chip analog power regulation bypass filter node for adc1 (see recommended bypass - figure 4 ) not muxed byp_a1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem (see recommended bypass - figure 4 ) not muxed byp_d0 can0_rx can0 receive b pb_15 can0_tx can0 transmit c pc_00 can1_rx can1 receive b pb_10 can1_tx can1 transmit b pb_11 cnt0_dg cnt0 count down and gate b pb_02 cnt0_outa cnt0 output divider a b pb_13 cnt0_outa cnt0 output divider a f pf_00 cnt0_outb cnt0 output divider b b pb_14 cnt0_outb cnt0 output divider b f pf_01 cnt0_ud cnt0 count up and direction b pb_01 cnt0_zm cnt0 count zero marker b pb_00 cnt1_dg cnt1 count down and gate b pb_05 cnt1_outa cnt1 output divider a e pe_14 cnt1_outb cnt1 output divider b e pe_15 preliminary technical data rev. prf | page 29 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f cnt1_ud cnt1 count up and direction b pb_04 cnt1_zm cnt1 count zero marker b pb_03 cnt2_dg cnt2 count down and gate e pe_10 cnt2_ud cnt2 count up and direction e pe_09 cnt2_zm cnt2 count zero marker e pe_08 cnt3_dg cnt3 count down and gate e pe_13 cnt3_ud cnt3 count up and direction e pe_12 cnt3_zm cnt3 count zero marker e pe_11 cptmr0_in0 cptmr0 capture timer0 input 0 b pb_07 cptmr0_in1 cptmr0 capture timer0 input 1 b pb_08 cptmr0_in2 cptmr0 capture timer0 input 2 b pb_09 eth0_crs emac0 carrier sense/rmii receive data valid e pe_09 eth0_mdc emac0 management channel clock e pe_11 eth0_mdio emac0 management channel serial data e pe_10 eth0_ptpauxin emac0 ptp auxiliary trigger input e pe_07 eth0_ptpclkin emac0 ptp clock input e pe_06 eth0_ptppps emac0 ptp pulse-per-second output e pe_08 eth0_refclk emac0 reference clock e pe_15 eth0_rxd0 emac0 receive data 0 f pf_00 eth0_rxd1 emac0 receive data 1 f pf_01 eth0_txd0 emac0 transmit data 0 e pe_12 eth0_txd1 emac0 transmit data 1 e pe_13 eth0_txen emac0 transmit enable e pe_14 gnd digital ground not muxed gnd gnd_ana0 analog ground return for vdd_ana0 (see recommended bypass - figure 4 ) not muxed gnd_ana0 gnd_ana1 analog ground return for vdd_ana1 (see recommended bypass - figure 4 ) not muxed gnd_ana1 gnd_ana2 analog ground (see recommended bypass - figure 4 ) not muxed gnd_ana2 gnd_ana3 analog ground (see recommended bypass - figure 4 ) not muxed gnd_ana3 gnd_vref0 ground return for vref0 (see recommended bypass filter- figure 4 ) not muxed gnd_vref0 gnd_vref1 ground return for vref1 (see recommended bypass filter- figure 4 ) not muxed gnd_vref1 jtg_tck/swclk jtg clock/serial wire clock not muxed jtg_tck/swclk jtg_tdi jtg serial data in not muxed jtg_tdi jtg_tdo/swo jtg serial data out/serial wire trace output not muxed jtg_tdo/swo jtg_tms/swdio jtg mode select/serial wire debug data i/o not muxed jtg_tms/swdio jtg_trst jtg reset not muxed jtg_trst pa_00-pa_15 port a positions 0 C 15 a pa_00 C pa_15 pb_00-pb_15 port b positions 0 C 15 b pb_00 C pb_15 pc_00-pc_15 port c positions 0 C 15 c pc_00 C pc_15 pd_00-pd_15 port d positions 0 C 15 d pd_00 C pd_15 pe_00-pe_15 port e positions 0 C 15 e pe_00 C pe_15 pf_00-pf_10 port f positions 0 C 10 f pf_00 C pf_10 pwm0_ah pwm0 channel a high side a pa_02 pwm0_al pwm0 channel a low side a pa_03 pwm0_bh pwm0 channel b high side a pa_04 pwm0_bl pwm0 channel b low side a pa_05 table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name rev. prf | page 30 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pwm0_ch pwm0 channel c high side a pa_06 pwm0_cl pwm0 channel c low side a pa_07 pwm0_dh pwm0 channel d high side b pb_00 pwm0_dl pwm0 channel d low side b pb_01 pwm0_sync pwm0 sync a pa_00 pwm0_trip0 pwm0 shutdown input 0 a pa_01 pwm1_ah pwm1 channel a high side a pa_12 pwm1_al pwm1 channel a low side a pa_13 pwm1_bh pwm1 channel b high side a pa_14 pwm1_bl pwm1 channel b low side a pa_15 pwm1_ch pwm1 channel c high side a pa_08 pwm1_cl pwm1 channel c low side a pa_09 pwm1_dh pwm1 channel d high side b pb_02 pwm1_dl pwm1 channel d low side b pb_03 pwm1_sync pwm1 sync a pa_10 pwm1_trip0 pwm1 shutdown input 0 a pa_11 pwm2_ah pwm2 channel a high side b pb_06 pwm2_al pwm2 channel a low side b pb_07 pwm2_bh pwm2 channel b high side b pb_08 pwm2_bl pwm2 channel b low side b pb_09 pwm2_ch pwm2 channel c high side c pc_03 pwm2_cl pwm2 channel c low side c pc_04 pwm2_dh pwm2 channel d high side c pc_05 pwm2_dl pwm2 channel d low side c pc_06 pwm2_sync pwm2 sync b pb_04 pwm2_trip0 pwm2 shutdown input 0 b pb_05 refcap output of bandgap generato r filter node (see recommended bypass filter - figure 4 ) not muxed refcap sinc0_clk0 sinc0 clock 0 b pb_10 sinc0_clk1 sinc0 clock 1 c pc_07 sinc0_d0 sinc0 data 0 b pb_11 sinc0_d1 sinc0 data 1 b pb_12 sinc0_d2 sinc0 data 2 b pb_13 sinc0_d3 sinc0 data 3 b pb_14 smc0_a01 smc0 address 1 b pb_13 smc0_a01 smc0 address 1 f pf_05 smc0_a02 smc0 address 2 b pb_14 smc0_a02 smc0 address 2 f pf_06 smc0_a03 smc0 address 3 b pb_15 smc0_a03 smc0 address 3 f pf_07 smc0_a04 smc0 address 4 c pc_00 smc0_a04 smc0 address 4 f pf_08 smc0_a05 smc0 address 5 c pc_01 smc0_a05 smc0 address 5 f pf_09 smc0_a06 smc0 address 6 d pd_08 smc0_a07 smc0 address 7 d pd_09 table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 31 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f smc0_a08 smc0 address 8 d pd_10 smc0_a09 smc0 address 9 d pd_11 smc0_a10 smc0 address 10 d pd_12 smc0_a11 smc0 address 11 d pd_13 smc0_a12 smc0 address 12 d pd_14 smc0_a13 smc0 address 13 d pd_15 smc0_a14 smc0 address 14 e pe_00 smc0_a15 smc0 address 15 e pe_01 smc0_a16 smc0 address 16 e pe_02 smc0_a17 smc0 address 17 e pe_03 smc0_a18 smc0 address 18 e pe_04 smc0_a19 smc0 address 19 e pe_05 smc0_a20 smc0 address 20 e pe_06 smc0_a21 smc0 address 21 e pe_07 smc0_a22 smc0 address 22 e pe_08 smc0_a23 smc0 address 23 e pe_09 smc0_a24 smc0 address 24 e pe_11 smc0_abe0 smc0 byte enable 0 f pf_10 smc0_abe1 smc0 byte enable 1 f pf_02 smc0_ams0 smc0 memory select 0 b pb_11 smc0_ams0 smc0 memory select 0 not muxed smc0_ams0 smc0_ams1 smc0 memory select 1 e pe_10 smc0_ams2 smc0 memory select 2 a pa_07 smc0_ams3 smc0 memory select 3 c pc_11 smc0_aoe smc0 output enable b pb_12 smc0_aoe smc0 output enable f pf_03 smc0_ardy smc0 asynchronous ready b pb_08 smc0_ardy smc0 asynchronous ready f pf_04 smc0_are smc0 read enable b pb_09 smc0_are smc0 read enable not muxed smc0_are smc0_awe smc0 write enable b pb_10 smc0_awe smc0 write enable not muxed smc0_awe smc0_d00 smc0 data 0 a pa_08 smc0_d00 smc0 data 0 c pc_08 smc0_d01 smc0 data 1 a pa_09 smc0_d01 smc0 data 1 c pc_09 smc0_d02 smc0 data 2 a pa_10 smc0_d02 smc0 data 2 c pc_10 smc0_d03 smc0 data 3 a pa_11 smc0_d03 smc0 data 3 c pc_11 smc0_d04 smc0 data 4 a pa_12 smc0_d04 smc0 data 4 c pc_12 smc0_d05 smc0 data 5 a pa_13 smc0_d05 smc0 data 5 c pc_13 smc0_d06 smc0 data 6 a pa_14 smc0_d06 smc0 data 6 c pc_14 table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name rev. prf | page 32 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data smc0_d07 smc0 data 7 a pa_15 smc0_d07 smc0 data 7 c pc_15 smc0_d08 smc0 data 8 b pb_00 smc0_d08 smc0 data 8 d pd_00 smc0_d09 smc0 data 9 b pb_01 smc0_d09 smc0 data 9 d pd_01 smc0_d10 smc0 data 10 b pb_02 smc0_d10 smc0 data 10 d pd_02 smc0_d11 smc0 data 11 b pb_03 smc0_d11 smc0 data 11 d pd_03 smc0_d12 smc0 data 12 b pb_04 smc0_d12 smc0 data 12 d pd_04 smc0_d13 smc0 data 13 b pb_05 smc0_d13 smc0 data 13 d pd_05 smc0_d14 smc0 data 14 b pb_06 smc0_d14 smc0 data 14 d pd_06 smc0_d15 smc0 data 15 b pb_07 smc0_d15 smc0 data 15 d pd_07 spi0_clk spi0 clock c pc_03 spi0_d2 spi0 data 2 b pb_10 spi0_d3 spi0 data 3 b pb_11 spi0_miso spi0 master in, slave out c pc_04 spi0_mosi spi0 master out, slave in c pc_05 spi0_rdy spi0 ready c pc_02 spi0_sel1 spi0 slave select output 1 c pc_06 spi0_sel2 spi0 slave select output 2 b pb_13 spi0_sel3 spi0 slave select output 3 b pb_14 spi0_ss spi0 slave select input b pb_14 spi1_clk spi1 clock c pc_12 spi1_miso spi1 master in, slave out c pc_13 spi1_mosi spi1 master out, slave in c pc_14 spi1_sel1 spi1 slave select output 1 c pc_15 spi1_sel2 spi1 slave select output 2 b pb_06 spi1_sel3 spi1 slave select output 3 b pb_07 spi1_ss spi1 slave select input c pc_15 spt0_aclk sport0 channel a clock b pb_00 spt0_aclk sport0 channel a clock e pe_00 spt0_ad0 sport0 channel a data 0 b pb_02 spt0_ad0 sport0 channel a data 0 e pe_02 spt0_ad1 sport0 channel a data 1 b pb_03 spt0_ad1 sport0 channel a data 1 e pe_03 spt0_afs sport0 channel a frame sync b pb_01 spt0_afs sport0 channel a frame sync e pe_01 spt0_atdv sport0 channel a tr ansmit data valid b pb_04 spt0_bclk sport0 channel b clock c pc_08 spt0_bd0 sport0 channel b data 0 c pc_10 table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 33 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f spt0_bd1 sport0 channel b data 1 c pc_11 spt0_bfs sport0 channel b frame sync c pc_09 spt0_btdv sport0 channel b transmit data valid b pb_12 spt1_aclk sport1 channel a clock a pa_00 spt1_ad0 sport1 channel a data 0 a pa_02 spt1_ad1 sport1 channel a data 1 a pa_03 spt1_afs sport1 channel a frame sync a pa_01 spt1_atdv sport1 channel a tr ansmit data valid b pb_15 spt1_bclk sport1 channel b clock a pa_04 spt1_bd0 sport1 channel b data 0 a pa_06 spt1_bd1 sport1 channel b data 1 a pa_07 spt1_bfs sport1 channel b frame sync a pa_05 spt1_btdv sport1 channel b transmit data valid c pc_00 sys_bmode0 boot mode control 0 not muxed sys_bmode0 sys_bmode1 boot mode control 1 not muxed sys_bmode1 sys_clkin clock/crystal input not muxed sys_clkin sys_clkout processor clock output not muxed sys_clkout sys_dswake0 deep sleep wakeup 0 c pc_06 sys_dswake1 deep sleep wakeup 1 c pc_07 sys_dswake2 deep sleep wakeup 2 b pb_14 sys_dswake3 deep sleep wakeup 3 b pb_13 sys_fault complementary fault output not muxed sys_fault sys_hwrst processor hardware reset control not muxed sys_hwrst sys_nmi non-maskable interrupt not muxed sys_nmi sys_resout reset output not muxed sys_resout sys_xtal crystal output not muxed sys_xtal tm0_aci1 timer0 alternate capture input 1 b pb_10 tm0_aci1 timer0 alternate capture input 1 d pd_13 tm0_aci2 timer0 alternate capture input 2 b pb_08 tm0_aci2 timer0 alternate capture input 2 d pd_12 tm0_aci3 timer0 alternate capture input 3 b pb_12 tm0_aci3 timer0 alternate capture input 3 d pd_11 tm0_aci4 timer0 alternate capture input 4 b pb_15 tm0_aci4 timer0 alternate capture input 4 d pd_10 tm0_aci5 timer0 alternate capture input 5 c pc_01 tm0_aci5 timer0 alternate capture input 5 d pd_09 tm0_aclk0 timer0 alternate clock 0 b pb_13 tm0_aclk1 timer0 alternate clock 1 b pb_11 tm0_aclk2 timer0 alternate clock 2 a pa_11 tm0_aclk3 timer0 alternate clock 3 a pa_10 tm0_aclk4 timer0 alternate clock 4 a pa_09 tm0_aclk5 timer0 alternate clock 5 a pa_08 tm0_clk timer0 clock b pb_06 tm0_clk timer0 clock d pd_08 tm0_tmr0 timer0 timer 0 b pb_07 tm0_tmr0 timer0 timer 0 d pd_00 table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name rev. prf | page 34 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data tm0_tmr1 timer0 timer 1 b pb_08 tm0_tmr1 timer0 timer 1 d pd_01 tm0_tmr2 timer0 timer 2 b pb_09 tm0_tmr2 timer0 timer 2 d pd_02 tm0_tmr3 timer0 timer 3 a pa_15 tm0_tmr3 timer0 timer 3 d pd_03 tm0_tmr4 timer0 timer 4 a pa_12 tm0_tmr4 timer0 timer 4 d pd_04 tm0_tmr5 timer0 timer 5 a pa_13 tm0_tmr5 timer0 timer 5 d pd_05 tm0_tmr6 timer0 timer 6 a pa_14 tm0_tmr6 timer0 timer 6 d pd_06 tm0_tmr7 timer0 timer 7 b pb_05 tm0_tmr7 timer0 timer 7 d pd_07 trace_clk embedded trace module clock b pb_00 trace_d00 embedded trace module data 0 b pb_01 trace_d01 embedded trace module data 1 b pb_02 trace_d02 embedded trace module data 2 b pb_03 trace_d03 embedded trace module data 3 c pc_02 trace_d03 embedded trace module data 3 f pf_02 twi0_scl twi0 serial clock not muxed twi0_scl twi0_sda twi0 serial data not muxed twi0_sda uart0_cts uart0 clear to send b pb_05 uart0_rts uart0 request to send b pb_04 uart0_rx uart0 receive c pc_01 uart0_tx uart0 transmit c pc_02 uart1_cts uart1 clear to send a pa_11 uart1_rts uart1 request to send c pc_07 uart1_rx uart1 receive b pb_08 uart1_rx uart1 receive b pb_15 uart1_tx uart1 transmit b pb_09 uart1_tx uart1 transmit c pc_00 uart2_rx uart2 receive b pb_12 uart2_tx uart2 transmit c pc_07 usb0_dm usb0 data - not muxed usb0_dm usb0_dp usb0 data + not muxed usb0_dp usb0_id usb0 otg id not muxed usb0_id usb0_vbc usb0 vbus control f pf_02 usb0_vbus usb0 bus voltage not muxed usb0_vbus vdd_ana0 analog power supply voltage 3.0v to 3.6v (see recommended bypass - figure 4 ) not muxed vdd_ana0 vdd_ana1 analog power supply voltage 3.0v to 3.6v. (see recommended bypass - figure 4 ) not muxed vdd_ana1 vdd_ext external voltage domain not muxed vdd_ext vdd_int internal voltage domain not muxed vdd_int vdd_vreg vreg supply voltage not muxed vdd_vreg table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 35 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f vref0 voltage reference for adc0. default configuration is output (see recommended bypass - figure 4 ) not muxed vref0 vref1 voltage reference for adc1. default configuration is output (see recommended bypass - figure 4 ) not muxed vref1 vreg_base voltage regulator base node not muxed vreg_base table 11. adsp-cm407f/ADSP-CM408F 176-lead lq fp signal descriptions (continued) signal name description port pin name rev. prf | page 36 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adsp-cm407f/ADSP-CM408F general- purpose i/o multiplexing for 176-lead lqfp table 12 through table 17 identify the pin functions that are multiplexed on the general-purp ose i/o pins of the 176-lead lqfp package. table 12. signal multiplexing for port a (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pa_00 pwm0_sync spt1_aclk pa_01 pwm0_trip0 spt1_afs pa_02 pwm0_ah spt1_ad0 pa_03 pwm0_al spt1_ad1 pa_04 pwm0_bh spt1_bclk pa_05 pwm0_bl spt1_bfs pa_06 pwm0_ch spt1_bd0 pa_07 pwm0_cl smc0_ams2 spt1_bd1 pa_08 pwm1_ch smc0_d00 tm0_aclk5 pa_09 pwm1_cl smc0_d01 tm0_aclk4 pa_10 pwm1_sync smc0_d02 tm0_aclk3 pa_11 pwm1_trip0 uart1_cts smc0_d03 tm0_aclk2 pa_12 pwm1_ah tm0_tmr4 smc0_d04 pa_13 pwm1_al tm0_tmr5 smc0_d05 pa_14 pwm1_bh tm0_tmr6 smc0_d06 pa_15 pwm1_bl tm0_tmr3 smc0_d07 table 13. signal multiplexing for port b (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pb_00 pwm0_dh trace_clk spt0_aclk smc0_d08 cnt0_zm pb_01 pwm0_dl trace_d00 spt0_afs smc0_d09 cnt0_ud pb_02 pwm1_dh trace_d01 spt0_ad0 smc0_d10 cnt0_dg pb_03 pwm1_dl trace_d02 spt0_ad1 smc0_d11 cnt1_zm pb_04 pwm2_sync uart0_rts spt0_atdv smc0_d12 cnt1_ud pb_05 pwm2_trip0 uart0_cts tm0_tmr7 smc0_d13 cnt1_dg pb_06 pwm2_ah tm0_clk spi1_sel2 smc0_d14 pb_07 pwm2_al tm0_tmr0 spi1_sel3 smc0_d15 cptmr0_in0 pb_08 pwm2_bh tm0_tmr1 uart1_rx smc0_ardy tm0_aci2/ cptmr0_in1 pb_09 pwm2_bl tm0_tmr2 uart1_tx smc0_are cptmr0_in2 pb_10 sinc0_clk0 spi0_d2 can1_rx smc0_awe tm0_aci1 pb_11 sinc0_d0 spi0_d3 can1_tx smc0_ams0 tm0_aclk1 pb_12 sinc0_d1 spt0_btdv uart2_rx smc0_aoe tm0_aci3 preliminary technical data rev. prf | page 37 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pb_13 sinc0_d2 cnt0_outa spi0_sel2 smc0_a01 tm0_aclk0/ sys_dswake3 pb_14 sinc0_d3 cnt0_outb spi0_sel3 smc0_a02 spi0_ss / sys_dswake2 pb_15 can0_rx spt1_atdv uart1_rx smc0_a03 tm0_aci4 table 13. signal multiplexing for port b (176-lead lqfp) (continued) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap table 14. signal multiplexing for port c (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pc_00 can0_tx spt1_btdv uart1_tx smc0_a04 pc_01 uart0_rx smc0_a05 tm0_aci5 pc_02 uart0_tx trace_d03 spi0_rdy pc_03 spi0_clk pwm2_ch pc_04 spi0_miso pwm2_cl pc_05 spi0_mosi pwm2_dh pc_06 spi0_sel1 pwm2_dl sys_dswake0 pc_07 sinc0_clk1 uart2_tx uart1_rts sys_dswake1 pc_08 spt0_bclk smc0_d00 pc_09 spt0_bfs smc0_d01 pc_10 spt0_bd0 smc0_d02 pc_11 smc0_ams3 spt0_bd1 smc0_d03 pc_12 spi1_clk smc0_d04 pc_13 spi1_miso smc0_d05 pc_14 spi1_mosi smc0_d06 pc_15 spi1_sel1 smc0_d07 spi1_ss table 15. signal multiplexing for port d (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pd_00 smc0_d08 tm0_tmr0 pd_01 smc0_d09 tm0_tmr1 pd_02 smc0_d10 tm0_tmr2 pd_03 smc0_d11 tm0_tmr3 pd_04 smc0_d12 tm0_tmr4 pd_05 smc0_d13 tm0_tmr5 pd_06 smc0_d14 tm0_tmr6 pd_07 smc0_d15 tm0_tmr7 pd_08 smc0_a06 tm0_clk pd_09 smc0_a07 tm0_aci5 pd_10 smc0_a08 tm0_aci4 pd_11 smc0_a09 tm0_aci3 pd_12 smc0_a10 tm0_aci2 rev. prf | page 38 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pd_13 smc0_a11 tm0_aci1 pd_14 smc0_a12 pd_15 smc0_a13 table 15. signal multiplexing for port d (176-lead lqfp) (continued) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap table 16. signal multiplexing for port e (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pe_00 smc0_a14 spt0_aclk pe_01 smc0_a15 spt0_afs pe_02 smc0_a16 spt0_ad0 pe_03 smc0_a17 spt0_ad1 pe_04 smc0_a18 pe_05 smc0_a19 pe_06 eth0_ptpclkin smc0_a20 pe_07 eth0_ptpauxin smc0_a21 pe_08 eth0_ptppps smc0_a22 cnt2_zm pe_09 eth0_crs smc0_a23 cnt2_ud pe_10 eth0_mdio smc0_ams1 cnt2_dg pe_11 eth0_mdc smc0_a24 cnt3_zm pe_12 eth0_txd0 cnt3_ud pe_13 eth0_txd1 cnt3_dg pe_14 eth0_txen cnt1_outa pe_15 eth0_refclk cnt1_outb table 17. signal multiplexing for port f (176-lead lqfp) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pf_00 eth0_rxd0 cnt0_outa pf_01 eth0_rxd1 cnt0_outb pf_02 usb0_vbc trace_d03 smc0_abe1 pf_03 smc0_aoe pf_04 smc0_ardy pf_05 smc0_a01 pf_06 smc0_a02 pf_07 smc0_a03 pf_08 smc0_a04 pf_09 smc0_a05 pf_10 smc0_abe0 preliminary technical data rev. prf | page 39 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm409f 212-ball bga signal descriptions the processors pin definitions are shown in table 18 . the col- umns in this table provide the following information: ? signal name - the signal name column in the table includes the signal name for every pin an d (where applica- ble) the gp i/o multiplexed pin function for every pin. ? description and notes - the description column in the table provides a verbose (descriptive) name for the signal. ?port - the general-purpose i/o port column in the table whether or not the signal is multiplexed with other signals on a general-purpose i/o port pin. ? pin name - the pin name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multi- plexed (if a general-purpose i/o pin). table 18. adsp-cm409f 212-ball bga signal descriptions signal name description port pin name adc0_vin00 channel 0 single -ended analog input for adc0 not muxed adc0_vin00 adc0_vin01 channel 1 single -ended analog input for adc0 not muxed adc0_vin01 adc0_vin02 channel 2 single -ended analog input for adc0 not muxed adc0_vin02 adc0_vin03 channel 3 single -ended analog input for adc0 not muxed adc0_vin03 adc0_vin04 channel 4 single -ended analog input for adc0 not muxed adc0_vin04 adc0_vin05 channel 5 single -ended analog input for adc0 not muxed adc0_vin05 adc0_vin06 channel 6 single -ended analog input for adc0 not muxed adc0_vin06 adc0_vin07 channel 7 single -ended analog input for adc0 not muxed adc0_vin07 adc0_vin08 channel 8 single -ended analog input for adc0 not muxed adc0_vin08 adc0_vin09 channel 9 single -ended analog input for adc0 not muxed adc0_vin09 adc0_vin10 channel 10 sing le-ended analog input for adc0 not muxed adc0_vin10 adc0_vin11 channel 11 sing le-ended analog input for adc0 not muxed adc0_vin11 adc1_vin00 channel 0 single -ended analog input for adc1 not muxed adc1_vin00 adc1_vin01 channel 1 single -ended analog input for adc1 not muxed adc1_vin01 adc1_vin02 channel 2 single -ended analog input for adc1 not muxed adc1_vin02 adc1_vin03 channel 3 single -ended analog input for adc1 not muxed adc1_vin03 adc1_vin04 channel 4 single -ended analog input for adc1 not muxed adc1_vin04 adc1_vin05 channel 5 single -ended analog input for adc1 not muxed adc1_vin05 adc1_vin06 channel 6 single -ended analog input for adc1 not muxed adc1_vin06 adc1_vin07 channel 7 single -ended analog input for adc1 not muxed adc1_vin07 adc1_vin08 channel 8 single -ended analog input for adc1 not muxed adc1_vin08 adc1_vin09 channel 9 single -ended analog input for adc1 not muxed adc1_vin09 adc1_vin10 channel 10 sing le-ended analog input for adc1 not muxed adc1_vin10 adc1_vin11 channel 11 sing le-ended analog input for adc1 not muxed adc1_vin11 byp_a0 on-chip analog power regulation bypass filter node for adc0 (see recommended bypass - figure 4 ) not muxed byp_a0 byp_a1 on-chip analog power regulation bypass filter node for adc1 (see recommended bypass - figure 4 ) not muxed byp_a1 byp_d0 on-chip digital power regulation bypass filter node for analog subsystem (see recommended bypass - figure 4 ) not muxed byp_d0 can0_rx can0 receive b pb_15 can0_tx can0 transmit c pc_00 can1_rx can1 receive b pb_10 can1_tx can1 transmit b pb_11 cnt0_dg cnt0 count down and gate b pb_02 cnt0_outa cnt0 output divider a b pb_13 rev. prf | page 40 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data cnt0_outa cnt0 output divider a f pf_00 cnt0_outb cnt0 output divider b b pb_14 cnt0_outb cnt0 output divider b f pf_01 cnt0_ud cnt0 count up and direction b pb_01 cnt0_zm cnt0 count zero marker b pb_00 cnt1_dg cnt1 count down and gate b pb_05 cnt1_outa cnt1 output divider a e pe_14 cnt1_outb cnt1 output divider b e pe_15 cnt1_ud cnt1 count up and direction b pb_04 cnt1_zm cnt1 count zero marker b pb_03 cnt2_dg cnt2 count down and gate e pe_10 cnt2_ud cnt2 count up and direction e pe_09 cnt2_zm cnt2 count zero marker e pe_08 cnt3_dg cnt3 count down and gate e pe_13 cnt3_ud cnt3 count up and direction e pe_12 cnt3_zm cnt3 count zero marker e pe_11 cptmr0_in0 cptmr0 capture timer0 input 0 b pb_07 cptmr0_in1 cptmr0 capture timer0 input 1 b pb_08 cptmr0_in2 cptmr0 capture timer0 input 2 b pb_09 dac0_vout analog voltage output 0 not muxed dac0_vout dac1_vout analog voltage output 1 not muxed dac1_vout eth0_crs emac0 carrier sense/rmii receive data valid e pe_09 eth0_mdc emac0 management channel clock e pe_11 eth0_mdio emac0 management channel serial data e pe_10 eth0_ptpauxin emac0 ptp auxiliary trigger input e pe_07 eth0_ptpclkin emac0 ptp clock input e pe_06 eth0_ptppps emac0 ptp pulse-per-second output e pe_08 eth0_refclk emac0 reference clock e pe_15 eth0_rxd0 emac0 receive data 0 f pf_00 eth0_rxd1 emac0 receive data 1 f pf_01 eth0_txd0 emac0 transmit data 0 e pe_12 eth0_txd1 emac0 transmit data 1 e pe_13 eth0_txen emac0 transmit enable e pe_14 gnd digital ground not muxed gnd gnd_ana analog ground returns for vdd_ana domain not muxed gnd_ana gnd_vref0 ground return for vref0 (see recommended bypass filter- figure 4 ) not muxed gnd_vref0 gnd_vref1 ground return for vref1 (see recommended bypass filter- figure 4 ) not muxed gnd_vref1 jtg_tck/swclk jtg clock/serial wi re clock not muxed jtg_tck/swclk jtg_tdi jtg serial data in not muxed jtg_tdi jtg_tdo/swo jtg serial data out/serial wire trace output not muxed jtg_tdo/swo jtg_tms/swdio jtg mode select/serial wire debug data i/o not muxed jtg_tms/swdio jtg_trst jtg reset not muxed jtg_trst pa_00-pa_15 port a positions 0 C 15 a pa_00 C pa_15 pb_00-pb_15 port b positions 0 C 15 b pb_00 C pb_15 pc_00-pc_15 port c positions 0 C 15 c pc_00 C pc_15 pd_00-pd_15 port d positions 0 C 15 d pd_00 C pd_15 table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 41 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pe_00-pe_15 port e positions 0 C 15 e pe_00 C pe_15 pf_00-pf_10 port f positions 0 C 15 f pf_00 C pf_10 pwm0_ah pwm0 channel a high side a pa_02 pwm0_al pwm0 channel a low side a pa_03 pwm0_bh pwm0 channel b high side a pa_04 pwm0_bl pwm0 channel b low side a pa_05 pwm0_ch pwm0 channel c high side a pa_06 pwm0_cl pwm0 channel c low side a pa_07 pwm0_dh pwm0 channel d high side b pb_00 pwm0_dl pwm0 channel d low side b pb_01 pwm0_sync pwm0 sync a pa_00 pwm0_trip0 pwm0 shutdown input 0 a pa_01 pwm1_ah pwm1 channel a high side a pa_12 pwm1_al pwm1 channel a low side a pa_13 pwm1_bh pwm1 channel b high side a pa_14 pwm1_bl pwm1 channel b low side a pa_15 pwm1_ch pwm1 channel c high side a pa_08 pwm1_cl pwm1 channel c low side a pa_09 pwm1_dh pwm1 channel d high side b pb_02 pwm1_dl pwm1 channel d low side b pb_03 pwm1_sync pwm1 sync a pa_10 pwm1_trip0 pwm1 shutdown input 0 a pa_11 pwm2_ah pwm2 channel a high side b pb_06 pwm2_al pwm2 channel a low side b pb_07 pwm2_bh pwm2 channel b high side b pb_08 pwm2_bl pwm2 channel b low side b pb_09 pwm2_ch pwm2 channel c high side c pc_03 pwm2_cl pwm2 channel c low side c pc_04 pwm2_dh pwm2 channel d high side c pc_05 pwm2_dl pwm2 channel d low side c pc_06 pwm2_sync pwm2 sync b pb_04 pwm2_trip0 pwm2 shutdown input 0 b pb_05 refcap output of bandgap generator filter node (see recommended bypass filter - figure 4 ) not muxed refcap sinc0_clk0 sinc0 clock 0 b pb_10 sinc0_clk1 sinc0 clock 1 c pc_07 sinc0_d0 sinc0 data 0 b pb_11 sinc0_d1 sinc0 data 1 b pb_12 sinc0_d2 sinc0 data 2 b pb_13 sinc0_d3 sinc0 data 3 b pb_14 smc0_a01 smc0 address 1 b pb_13 smc0_a01 smc0 address 1 f pf_05 smc0_a02 smc0 address 2 b pb_14 smc0_a02 smc0 address 2 f pf_06 smc0_a03 smc0 address 3 b pb_15 smc0_a03 smc0 address 3 f pf_07 table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name rev. prf | page 42 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data smc0_a04 smc0 address 4 c pc_00 smc0_a04 smc0 address 4 f pf_08 smc0_a05 smc0 address 5 c pc_01 smc0_a05 smc0 address 5 f pf_09 smc0_a06 smc0 address 6 d pd_08 smc0_a07 smc0 address 7 d pd_09 smc0_a08 smc0 address 8 d pd_10 smc0_a09 smc0 address 9 d pd_11 smc0_a10 smc0 address 10 d pd_12 smc0_a11 smc0 address 11 d pd_13 smc0_a12 smc0 address 12 d pd_14 smc0_a13 smc0 address 13 d pd_15 smc0_a14 smc0 address 14 e pe_00 smc0_a15 smc0 address 15 e pe_01 smc0_a16 smc0 address 16 e pe_02 smc0_a17 smc0 address 17 e pe_03 smc0_a18 smc0 address 18 e pe_04 smc0_a19 smc0 address 19 e pe_05 smc0_a20 smc0 address 20 e pe_06 smc0_a21 smc0 address 21 e pe_07 smc0_a22 smc0 address 22 e pe_08 smc0_a23 smc0 address 23 e pe_09 smc0_a24 smc0 address 24 e pe_11 smc0_abe0 smc0 byte enable 0 f pf_10 smc0_abe1 smc0 byte enable 1 f pf_02 smc0_ams0 smc0 memory select 0 b pb_11 smc0_ams0 smc0 memory select 0 not muxed smc0_ams0 smc0_ams1 smc0 memory select 1 e pe_10 smc0_ams2 smc0 memory select 2 a pa_07 smc0_ams3 smc0 memory select 3 c pc_11 smc0_aoe smc0 output enable b pb_12 smc0_aoe smc0 output enable f pf_03 smc0_ardy smc0 asynchronous ready b pb_08 smc0_ardy smc0 asynchronous ready f pf_04 smc0_are smc0 read enable b pb_09 smc0_are smc0 read enable not muxed smc0_are smc0_awe smc0 write enable b pb_10 smc0_awe smc0 write enable not muxed smc0_awe smc0_d00 smc0 data 0 a pa_08 smc0_d00 smc0 data 0 c pc_08 smc0_d01 smc0 data 1 a pa_09 smc0_d01 smc0 data 1 c pc_09 smc0_d02 smc0 data 2 a pa_10 smc0_d02 smc0 data 2 c pc_10 smc0_d03 smc0 data 3 a pa_11 smc0_d03 smc0 data 3 c pc_11 table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 43 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f smc0_d04 smc0 data 4 a pa_12 smc0_d04 smc0 data 4 c pc_12 smc0_d05 smc0 data 5 a pa_13 smc0_d05 smc0 data 5 c pc_13 smc0_d06 smc0 data 6 a pa_14 smc0_d06 smc0 data 6 c pc_14 smc0_d07 smc0 data 7 a pa_15 smc0_d07 smc0 data 7 c pc_15 smc0_d08 smc0 data 8 b pb_00 smc0_d08 smc0 data 8 d pd_00 smc0_d09 smc0 data 9 b pb_01 smc0_d09 smc0 data 9 d pd_01 smc0_d10 smc0 data 10 b pb_02 smc0_d10 smc0 data 10 d pd_02 smc0_d11 smc0 data 11 b pb_03 smc0_d11 smc0 data 11 d pd_03 smc0_d12 smc0 data 12 b pb_04 smc0_d12 smc0 data 12 d pd_04 smc0_d13 smc0 data 13 b pb_05 smc0_d13 smc0 data 13 d pd_05 smc0_d14 smc0 data 14 b pb_06 smc0_d14 smc0 data 14 d pd_06 smc0_d15 smc0 data 15 b pb_07 smc0_d15 smc0 data 15 d pd_07 spi0_clk spi0 clock c pc_03 spi0_d2 spi0 data 2 b pb_10 spi0_d3 spi0 data 3 b pb_11 spi0_miso spi0 master in, slave out c pc_04 spi0_mosi spi0 master out, slave in c pc_05 spi0_rdy spi0 ready c pc_02 spi0_sel1 spi0 slave select output 1 c pc_06 spi0_sel2 spi0 slave select output 2 b pb_13 spi0_sel3 spi0 slave select output 3 b pb_14 spi0_ss spi0 slave select input b pb_14 spi1_clk spi1 clock c pc_12 spi1_miso spi1 master in, slave out c pc_13 spi1_mosi spi1 master out, slave in c pc_14 spi1_sel1 spi1 slave select output 1 c pc_15 spi1_sel2 spi1 slave select output 2 b pb_06 spi1_sel3 spi1 slave select output 3 b pb_07 spi1_ss spi1 slave select input c pc_15 spt0_aclk sport0 channel a clock b pb_00 spt0_aclk sport0 channel a clock e pe_00 spt0_ad0 sport0 channel a data 0 b pb_02 spt0_ad0 sport0 channel a data 0 e pe_02 spt0_ad1 sport0 channel a data 1 b pb_03 table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name rev. prf | page 44 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data spt0_ad1 sport0 channel a data 1 e pe_03 spt0_afs sport0 channe l a frame sync b pb_01 spt0_afs sport0 channel a frame sync e pe_01 spt0_atdv sport0 channel a transmit data valid b pb_04 spt0_bclk sport0 channel b clock c pc_08 spt0_bd0 sport0 channel b data 0 c pc_10 spt0_bd1 sport0 channel b data 1 c pc_11 spt0_bfs sport0 channel b frame sync c pc_09 spt0_btdv sport0 channel b transmit data valid b pb_12 spt1_aclk sport1 channel a clock a pa_00 spt1_ad0 sport1 channel a data 0 a pa_02 spt1_ad1 sport1 channel a data 1 a pa_03 spt1_afs sport1 channel a frame sync a pa_01 spt1_atdv sport1 channel a transmit data valid b pb_15 spt1_bclk sport1 channel b clock a pa_04 spt1_bd0 sport1 channel b data 0 a pa_06 spt1_bd1 sport1 channel b data 1 a pa_07 spt1_bfs sport1 channel b frame sync a pa_05 spt1_btdv sport1 channel b transmit data valid c pc_00 sys_bmode0 boot mode control 0 not muxed sys_bmode0 sys_bmode1 boot mode control 1 not muxed sys_bmode1 sys_clkin clock/crystal input not muxed sys_clkin sys_clkout processor clock output not muxed sys_clkout sys_dswake0 deep sleep wakeup 0 c pc_06 sys_dswake1 deep sleep wakeup 1 c pc_07 sys_dswake2 deep sleep wakeup 2 b pb_14 sys_dswake3 deep sleep wakeup 3 b pb_13 sys_fault complementary fault output not muxed sys_fault sys_hwrst processor hardware reset control not muxed sys_hwrst sys_nmi non-maskable interrupt not muxed sys_nmi sys_resout reset output not muxed sys_resout sys_xtal crystal output not muxed sys_xtal tm0_aci1 timer0 alternate capture input 1 b pb_10 tm0_aci1 timer0 alternate capture input 1 d pd_13 tm0_aci2 timer0 alternate capture input 2 b pb_08 tm0_aci2 timer0 alternate capture input 2 d pd_12 tm0_aci3 timer0 alternate capture input 3 b pb_12 tm0_aci3 timer0 alternate capture input 3 d pd_11 tm0_aci4 timer0 alternate capture input 4 b pb_15 tm0_aci4 timer0 alternate capture input 4 d pd_10 tm0_aci5 timer0 alternate capture input 5 c pc_01 tm0_aci5 timer0 alternate capture input 5 d pd_09 tm0_aclk0 timer0 alternate clock 0 b pb_13 tm0_aclk1 timer0 alternate clock 1 b pb_11 tm0_aclk2 timer0 alternate clock 2 a pa_11 tm0_aclk3 timer0 alternate clock 3 a pa_10 table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 45 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f tm0_aclk4 timer0 alternate clock 4 a pa_09 tm0_aclk5 timer0 alternate clock 5 a pa_08 tm0_clk timer0 clock b pb_06 tm0_clk timer0 clock d pd_08 tm0_tmr0 timer0 timer 0 b pb_07 tm0_tmr0 timer0 timer 0 d pd_00 tm0_tmr1 timer0 timer 1 b pb_08 tm0_tmr1 timer0 timer 1 d pd_01 tm0_tmr2 timer0 timer 2 b pb_09 tm0_tmr2 timer0 timer 2 d pd_02 tm0_tmr3 timer0 timer 3 a pa_15 tm0_tmr3 timer0 timer 3 d pd_03 tm0_tmr4 timer0 timer 4 a pa_12 tm0_tmr4 timer0 timer 4 d pd_04 tm0_tmr5 timer0 timer 5 a pa_13 tm0_tmr5 timer0 timer 5 d pd_05 tm0_tmr6 timer0 timer 6 a pa_14 tm0_tmr6 timer0 timer 6 d pd_06 tm0_tmr7 timer0 timer 7 b pb_05 tm0_tmr7 timer0 timer 7 d pd_07 trace_clk embedded trace module clock b pb_00 trace_d00 embedded trace module data 0 b pb_01 trace_d01 embedded trace module data 1 b pb_02 trace_d02 embedded trace module data 2 b pb_03 trace_d03 embedded trace module data 3 c pc_02 trace_d03 embedded trace module data 3 f pf_02 twi0_scl twi0 serial clock not muxed twi0_scl twi0_sda twi0 serial data not muxed twi0_sda uart0_cts uart0 clear to send b pb_05 uart0_rts uart0 request to send b pb_04 uart0_rx uart0 receive c pc_01 uart0_tx uart0 transmit c pc_02 uart1_cts uart1 clear to send a pa_11 uart1_rts uart1 request to send c pc_07 uart1_rx uart1 receive b pb_08 uart1_rx uart1 receive b pb_15 uart1_tx uart1 transmit b pb_09 uart1_tx uart1 transmit c pc_00 uart2_rx uart2 receive b pb_12 uart2_tx uart2 transmit c pc_07 usb0_dm usb0 data - not muxed usb0_dm usb0_dp usb0 data + not muxed usb0_dp usb0_id usb0 otg id not muxed usb0_id usb0_vbc usb0 vbus control f pf_02 usb0_vbus usb0 bus voltage not muxed usb0_vbus table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name rev. prf | page 46 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data vdd_ana0 analog power supply voltage 3.0v to 3.6v (see recommended bypass - figure 4 ) not muxed vdd_ana0 vdd_ana1 analog power supply voltage 3.0v to 3.6v. (see recommended bypass - figure 4 ) not muxed vdd_ana1 vdd_ext external voltage domain not muxed vdd_ext vdd_int internal voltage domain not muxed vdd_int vdd_vreg vreg supply voltage not muxed vdd_vreg vref0 voltage reference for adc0. default configuration is output (see recommended bypass - figure 4 ) not muxed vref0 vref1 voltage reference for adc1. default configuration is output (see recommended bypass - figure 4 ) not muxed vref1 vreg_base voltage regulator base node not muxed vreg_base table 18. adsp-cm409f 212-ball bga signal descriptions (continued) signal name description port pin name preliminary technical data rev. prf | page 47 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm409f general-purpose i/ o multiplexing for 212-ball bga table 19 through table 24 identify the pin functions that are multiplexed on the general-pu rpose i/o pins of the 212-ball bga package. table 19. signal multiplexing for port a (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pa_00 pwm0_sync spt1_aclk pa_01 pwm0_trip0 spt1_afs pa_02 pwm0_ah spt1_ad0 pa_03 pwm0_al spt1_ad1 pa_04 pwm0_bh spt1_bclk pa_05 pwm0_bl spt1_bfs pa_06 pwm0_ch spt1_bd0 pa_07 pwm0_cl smc0_ams2 spt1_bd1 pa_08 pwm1_ch smc0_d00 tm0_aclk5 pa_09 pwm1_cl smc0_d01 tm0_aclk4 pa_10 pwm1_sync smc0_d02 tm0_aclk3 pa_11 pwm1_trip0 uart1_cts smc0_d03 tm0_aclk2 pa_12 pwm1_ah tm0_tmr4 smc0_d04 pa_13 pwm1_al tm0_tmr5 smc0_d05 pa_14 pwm1_bh tm0_tmr6 smc0_d06 pa_15 pwm1_bl tm0_tmr3 smc0_d07 table 20. signal multiplexing for port b (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pb_00 pwm0_dh trace_clk spt0_aclk smc0_d08 cnt0_zm pb_01 pwm0_dl trace_d00 spt0_afs smc0_d09 cnt0_ud pb_02 pwm1_dh trace_d01 spt0_ad0 smc0_d10 cnt0_dg pb_03 pwm1_dl trace_d02 spt0_ad1 smc0_d11 cnt1_zm pb_04 pwm2_sync uart0_rts spt0_atdv smc0_d12 cnt1_ud pb_05 pwm2_trip0 uart0_cts tm0_tmr7 smc0_d13 cnt1_dg pb_06 pwm2_ah tm0_clk spi1_sel2 smc0_d14 pb_07 pwm2_al tm0_tmr0 spi1_sel3 smc0_d15 cptmr0_in0 pb_08 pwm2_bh tm0_tmr1 uart1_rx smc0_ardy tm0_aci2/ cptmr0_in1 pb_09 pwm2_bl tm0_tmr2 uart1_tx smc0_are cptmr0_in2 pb_10 sinc0_clk0 spi0_d2 can1_rx smc0_awe tm0_aci1 pb_11 sinc0_d0 spi0_d3 can1_tx smc0_ams0 tm0_aclk1 pb_12 sinc0_d1 spt0_btdv uart2_rx smc0_aoe tm0_aci3 pb_13 sinc0_d2 cnt0_outa spi0_sel2 smc0_a01 tm0_aclk0/ sys_dswake3 pb_14 sinc0_d3 cnt0_outb spi0_sel3 smc0_a02 spi0_ss / sys_dswake2 pb_15 can0_rx spt1_atdv uart1_rx smc0_a03 tm0_aci4 rev. prf | page 48 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table 21. signal multiplexing for port c (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pc_00 can0_tx spt1_btdv uart1_tx smc0_a04 pc_01 uart0_rx smc0_a05 tm0_aci5 pc_02 uart0_tx trace_d03 spi0_rdy pc_03 spi0_clk pwm2_ch pc_04 spi0_miso pwm2_cl pc_05 spi0_mosi pwm2_dh pc_06 spi0_sel1 pwm2_dl sys_dswake0 pc_07 sinc0_clk1 uart2_tx uart1_rts sys_dswake1 pc_08 spt0_bclk smc0_d00 pc_09 spt0_bfs smc0_d01 pc_10 spt0_bd0 smc0_d02 pc_11 smc0_ams3 spt0_bd1 smc0_d03 pc_12 spi1_clk smc0_d04 pc_13 spi1_miso smc0_d05 pc_14 spi1_mosi smc0_d06 pc_15 spi1_sel1 smc0_d07 spi1_ss table 22. signal multiplexing for port d (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pd_00 smc0_d08 tm0_tmr0 pd_01 smc0_d09 tm0_tmr1 pd_02 smc0_d10 tm0_tmr2 pd_03 smc0_d11 tm0_tmr3 pd_04 smc0_d12 tm0_tmr4 pd_05 smc0_d13 tm0_tmr5 pd_06 smc0_d14 tm0_tmr6 pd_07 smc0_d15 tm0_tmr7 pd_08 smc0_a06 tm0_clk pd_09 smc0_a07 tm0_aci5 pd_10 smc0_a08 tm0_aci4 pd_11 smc0_a09 tm0_aci3 pd_12 smc0_a10 tm0_aci2 pd_13 smc0_a11 tm0_aci1 pd_14 smc0_a12 pd_15 smc0_a13 preliminary technical data rev. prf | page 49 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f table 23. signal multiplexing for port e (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pe_00 smc0_a14 spt0_aclk pe_01 smc0_a15 spt0_afs pe_02 smc0_a16 spt0_ad0 pe_03 smc0_a17 spt0_ad1 pe_04 smc0_a18 pe_05 smc0_a19 pe_06 eth0_ptpclkin smc0_a20 pe_07 eth0_ptpauxin smc0_a21 pe_08 eth0_ptppps smc0_a22 cnt2_zm pe_09 eth0_crs smc0_a23 cnt2_ud pe_10 eth0_mdio smc0_ams1 cnt2_dg pe_11 eth0_mdc smc0_a24 cnt3_zm pe_12 eth0_txd0 cnt3_ud pe_13 eth0_txd1 cnt3_dg pe_14 eth0_txen cnt1_outa pe_15 eth0_refclk cnt1_outb table 24. signal multiplexing for port f (212-ball bga) signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function 3 multiplexed function input tap pf_00 eth0_rxd0 cnt0_outa pf_01 eth0_rxd1 cnt0_outb pf_02 usb0_vbc trace_d03 smc0_abe1 pf_03 smc0_aoe pf_04 smc0_ardy pf_05 smc0_a01 pf_06 smc0_a02 pf_07 smc0_a03 pf_08 smc0_a04 pf_09 smc0_a05 pf_10 smc0_abe0 rev. prf | page 50 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adsp-cm40xf designer quick reference table 25 provides a quick reference summary of pin related information for circuit board desi gn. the columns in this table provide the following information: ? signal name - the signal name column in the table includes the signal name for every pin an d (where applica- ble) the gp i/o multiplexed pin function for every pin. ?type - the pin type column in the table identifies the i/o type or supply type of the pi n. the abbreviations used in this column are na (none), i/o (input/output), a (analog), s (supply), and g (ground). ?driver type - the driver type column in the table identi- fies the driver type used by the pin. the driver types are defined in the output drive currents section of this data sheet. ?int term - the internal termination column in the table specifies the termination presen t when the processor is not in the reset state. the abbrevia tions used in this column are wk (weak keeper, weak ly retains previous value driven on the pin), pu (pull-up), or pd (pull-down). ? reset term - the reset termination column in the table specifies the termination presen t when the processor is in the reset state. the abbreviations used in this column are wk (weak keeper, weakly retain s previous value driven on the pin), pu (pull-up), or pd (pull-down). ? reset drive - the reset drive column in the table specifies the active drive on the signal when the processor is in the reset state. ? power domain - the power domain column in the table specifies the power supply domain in which the signal resides. ?description and notes - the description and notes column in the table identifies any sp ecial requirements or charac- teristics for the signal. if no special requirements are listed the signal may be left unconnected if it is not used. also, for multiplexed general-purpose i/ o pins, this column identi- fies the functions available on the pin. table 25. adsp-cm40xf designer quick reference signal name type driver type int term reset term reset drive power domain description and notes adc0_vin00 a na none none none vdd_ana desc: ch annel 0 single-ended analog input for adc0 notes: no notes adc0_vin01 a na none none none vdd_ana desc: ch annel 1 single-ended analog input for adc0 notes: no notes adc0_vin02 a na none none none vdd_ana desc: ch annel 2 single-ended analog input for adc0 notes: no notes adc0_vin03 a na none none none vdd_ana desc: ch annel 3 single-ended analog input for adc0 notes: no notes adc0_vin04 a na none none none vdd_ana desc: ch annel 4 single-ended analog input for adc0 notes: no notes adc0_vin05 a na none none none vdd_ana desc: ch annel 5 single-ended analog input for adc0 notes: no notes adc0_vin06 a na none none none vdd_ana desc: ch annel 6 single-ended analog input for adc0 notes: no notes adc0_vin07 a na none none none vdd_ana desc: ch annel 7 single-ended analog input for adc0 notes: no notes adc0_vin08 a na none none none vdd_ana desc: ch annel 8 single-ended analog input for adc0 notes: no notes preliminary technical data rev. prf | page 51 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adc0_vin09 a na none none none vdd_ana desc: channel 9 single-ended analog input for adc0 notes: no notes adc0_vin10 a na none none none vdd_ana desc: ch annel 10 single-ended analog input for adc0 notes: no notes adc0_vin11 a na none none none vdd_ana desc: ch annel 11 single-ended analog input for adc0 notes: no notes adc1_vin00 a na none none none vdd_ana desc: channel 0 single-ended analog input for adc1 notes: no notes adc1_vin01 a na none none none vdd_ana desc: channel 1 single-ended analog input for adc1 notes: no notes adc1_vin02 a na none none none vdd_ana desc: channel 2 single-ended analog input for adc1 notes: no notes adc1_vin03 a na none none none vdd_ana desc: channel 3 single-ended analog input for adc1 notes: no notes adc1_vin04 a na none none none vdd_ana desc: channel 4 single-ended analog input for adc1 notes: no notes adc1_vin05 a na none none none vdd_ana desc: channel 5 single-ended analog input for adc1 notes: no notes adc1_vin06 a na none none none vdd_ana desc: channel 6 single-ended analog input for adc1 notes: no notes adc1_vin07 a na none none none vdd_ana desc: channel 7 single-ended analog input for adc1 notes: no notes adc1_vin08 a na none none none vdd_ana desc: channel 8 single-ended analog input for adc1 notes: no notes adc1_vin09 a na none none none vdd_ana desc: channel 9 single-ended analog input for adc1 notes: no notes adc1_vin10 a na none none none vdd_ana desc: ch annel 10 single-ended analog input for adc1 notes: no notes adc1_vin11 a na none none none vdd_ana desc: ch annel 11 single-ended analog input for adc1 notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes rev. prf | page 52 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data byp_a0 a na none none h vdd_ana desc: on-chip analog power regulation bypass filter node for adc0 (see recommended bypass - figure 4 ) notes: this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor byp_a1 a na none none h vdd_ana desc: on-chip analog power regulation bypass filter node for adc1 (see recommended bypass - figure 4 ) notes: this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor byp_d0 a na none none h vdd_ext desc: on-chip digital power regulation bypass filter node for analog subsystem (see recom- mended bypass - figure 4 ) notes: this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor dac0_vout a na none none l vdd_ana desc: analog voltage output 0 notes: no notes dac1_vout a na none none l vdd_ana desc: analog voltage output 1 notes: no notes gnd g na none none none vdd_ext and vdd_int desc: digital ground notes: no notes gnd_ana g na none none none vd d_ana desc: analog ground returns for vdd_ana domain notes: no notes gnd_ana0 g na none none none vdd_ana desc: an alog ground return for vdd_ana0 (see recommended bypass - figure 4 ) notes: no notes gnd_ana1 g na none none none vdd_ana desc: an alog ground return for vdd_ana1 (see recommended bypass - figure 4 ) notes: no notes gnd_ana2 g na none none none vdd_ana desc : analog ground (see recommended bypass - figure 4 ) notes: no notes gnd_ana3 g na none none none vdd_ana desc : analog ground (see recommended bypass - figure 4 ) notes: no notes gnd_vref0 g na none none none vdd_ana desc: ground return for vref0 (see recom- mended bypass filter- figure 4 ) notes: no notes gnd_vref1 g na none none none vdd_ana desc: ground return for vref1 (see recom- mended bypass filter- figure 4 ) notes: no notes jtg_tck/swclk i/o na pd pd none vdd_ext desc: jtg clock/serial wire clock notes: no notes jtg_tdi i/o na pu pu none vdd_ext desc: jtg serial data in notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes preliminary technical data rev. prf | page 53 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f jtg_tdo/swo i/o a none none none vdd_ext desc: jtg serial data out/serial wire trace output notes: no notes jtg_tms/swdio i/o a pu pu none vdd_ext desc: jtg mode select/serial wire debug data i/o notes: no notes jtg_trst i/o a pu pu none vdd_ext desc: jtg reset notes: requires pull-up if using trace functionality; otherwise pull-down should be connected pa_00 i/o a pu pu none vdd_ext desc: pa position 0 | pwm0 sync | sport1 channel a clock notes: no notes pa_01 i/o a pu pu none vdd_ext desc: pa position 1 | pwm0 shutdown input 0 | sport1 channel a frame sync notes: no notes pa_02 i/o a pu pu none vdd_ext desc: pa position 2 | pwm0 channel a high side | sport1 channel a data 0 notes: no notes pa_03 i/o a pu pu none vdd_ext desc: pa position 3 | pwm0 channel a low side | sport1 channel a data 1 notes: no notes pa_04 i/o a pu pu none vdd_ext desc: pa position 4 | pwm0 channel b high side | sport1 channel b clock notes: no notes pa_05 i/o a pu pu none vdd_ext desc: pa position 5 | pwm0 channel b low side | sport1 channel b frame sync notes: no notes pa_06 i/o a pu pu none vdd_ext desc: pa position 6 | pwm0 channel c high side | sport1 channel b data 0 notes: no notes pa_07 i/o a pu pu none vdd_ext desc: pa posi tion 7 | pwm0 channel c low side | smc0 memory select 2 | sport1 channel b data 1 notes: no notes pa_08 i/o a pu pu none vdd_ext desc: pa position 8 | pwm1 channel c high side | smc0 data 0 | tm0 timer5 alternate clock notes: no notes pa_09 i/o a pu pu none vdd_ext desc: pa posi tion 9 | pwm1 channel c low side | smc0 data 1 | tm0 timer4 alternate clock notes: no notes pa_10 i/o a pu pu none vdd_ext desc: pa position 10 | pwm1 sync | smc0 data 2 | tm0 timer3 alternate clock notes: no notes pa_11 i/o a pu pu none vdd_ext desc: pa posi tion 11 | pwm1 shutdown input 0 | uart1 clear to send | smc0 data 3 | tm0 timer2 alternate clock notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes rev. prf | page 54 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pa_12 i/o a pu pu none vdd_ext desc: pa position 12 | pwm1 channel a high side | tm0 timer 4 | smc0 data 4 notes: no notes pa_13 i/o a pu pu none vdd_ext desc: pa position 13 | pwm1 channel a low side | tm0 timer 5 | smc0 data 5 notes: no notes pa_14 i/o a pu pu none vdd_ext desc: pa position 14 | pwm1 channel b high side | tm0 timer 6 | smc0 data 6 notes: no notes pa_15 i/oa pupunonevdd_extdesc: pa posi tion 15 | pwm1 channel b low side | tm0 timer 3 | smc0 data 7 notes: no notes pb_00 i/o a pu pu none vdd_ext desc: pb position 0 | pwm0 channel d high side | embedded trace module clock | sport0 channel a clock | smc0 data 8 | cnt0 count zero marker notes: no notes pb_01 i/o a pu pu none vdd_ext desc: pb position 1 | pwm0 channel d low side | embedded trace module data 0 | sport0 channel a frame sync | smc0 data 9 | cnt0 count up and direction notes: no notes pb_02 i/o a pu pu none vdd_ext desc: pb position 2 | pwm1 channel d high side | embedded trace module data 1 | sport0 channel a data 0 | smc0 data 10 | cnt0 count down and gate notes: no notes pb_03 i/o a pu pu none vdd_ext desc: pb position 3 | pwm1 channel d low side | embedded trace module data 2 | sport0 channel a data 1 | smc0 data 11 | cnt1 count zero marker notes: no notes pb_04 i/oa pupunonevdd_extdesc: pb position 4 | pwm2 sync | uart0 request to send | sport0 channel a transmit data valid | smc0 data 12 | cnt1 count up and direction notes: no notes pb_05 i/o a pu pu none vdd_ext desc: pb position 5 | pwm2 shutdown input 0 | uart0 clear to send | tm0 timer 7 | smc0 data 13 | cnt1 count down and gate notes: no notes pb_06 i/o a pu pu none vdd_ext desc: pb position 6 | pwm2 channel a high side | tm0 common clock | spi1 slave select output 2 | smc0 data 14 notes: no notes pb_07 i/o a pu pu none vdd_ext desc: pb position 7 | pwm2 channel a low side | tm0 timer 0 | spi1 slave select output 3 | smc0 data 15 | capture timer0 input 0 notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes preliminary technical data rev. prf | page 55 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pb_08 i/o a pu pu none vdd_ext desc: pb position 8 | pwm2 channel b high side | tm0 timer 1 | uart1 receive | smc0 asynchronous ready | tm0 timer2 alternate capture input | capture timer0 input 1 notes: no notes pb_09 i/o a pu pu none vdd_ext desc: pb position 9 | pwm2 channel b low side | tm0 timer 2 | uart1 transmit | smc0 read enable | capture timer0 input 2 notes: no notes pb_10 i/o a pu pu none vdd_ext desc: pb position 10 | sinc0 clock 0 | spi0 data 2 | can1 receive | smc0 write enable | tm0 timer1 alternate capture input notes: no notes pb_11 i/o a pu pu none vdd_ext desc: pb position 11 | sinc0 data 0 | spi0 data 3 | can1 transmit | smc0 memory select 0 | tm0 timer1 alternate clock notes: no notes pb_12 i/o a pu pu none vdd_ext desc: pb position 12 | sinc0 data 1 | sport0 channel b transmit data valid | uart2 receive | smc0 output enable | tm0 timer3 alternate capture input notes: no notes pb_13 i/o a pu pu none vdd_ext desc: pb position 13 | sinc0 data 2 | cnt0 output divider a | spi0 slave select output 2 | smc0 address 1 | sys0 deep sleep wakeup 3 | tm0 timer0 alternate clock notes: no notes pb_14 i/o a pu pu none vdd_ext desc: pb position 14 | sinc0 data 3 | cnt0 output divider b | spi0 slave select output 3 | smc0 address 2 | sys0 deep sleep wakeup 2 | spi0 slave select input notes: no notes pb_15 i/o a pu pu none vdd_ext desc: pb position 15 | can0 receive | sport1 channel a transmit data valid | uart1 receive | smc0 address 3 | tm0 timer4 alternate capture input notes: no notes pc_00 i/o a pu pu none vdd_ext desc: pc position 0 | can0 transmit | sport1 channel b transmit data valid | uart1 transmit | smc0 address 4 notes: no notes pc_01 i/o a pu pu none vdd_ext desc: pc position 1 | uart0 receive | smc0 address 5 | tm0 timer5 alternate capture input notes: no notes pc_02 i/o a pu pu none vdd_ext desc: pc position 2 | uart0 transmit | embedded trace module data 3 | spi0 ready notes: no notes pc_03 i/o a pu pu none vdd_ext desc: pc position 3 | spi0 clock | pwm2 channel c high side notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes rev. prf | page 56 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pc_04 i/oa pupunonevdd_extdesc: pc positi on 4 | spi0 master in, slave out | pwm2 channel c low side notes: no notes pc_05 i/o a pu pu none vdd_ext desc: pc position 5 | spi0 master out, slave in | pwm2 channel d high side notes: no notes pc_06 i/oa pupunonevdd_extdesc: pc positi on 6 | spi0 slave select output 1 | pwm2 channel d low side | sys0 deep sleep wakeup 0 notes: no notes pc_07 i/o a pu pu none vdd_ext desc: pc position 7 | sinc0 clock 1 | uart2 transmit | uart1 request to send | sys0 deep sleep wakeup 1 notes: no notes pc_08 i/o a pu pu none vdd_ext desc: pc position 8 | sport0 channel b clock | smc0 data 0 notes: no notes pc_09 i/o a pu pu none vdd_ext desc: pc position 9 | sport0 channel b frame sync | smc0 data 1 notes: no notes pc_10 i/o a pu pu none vdd_ext desc: pc position 10 | sport0 channel b data 0 | smc0 data 2 notes: no notes pc_11 i/o a pu pu none vdd_ext desc: pc position 11 | smc0 memory select 3 | spt0 channel b data 1 | smc0 data 3 notes: no notes pc_12 i/o a pu pu none vdd_ext desc: pc position 12 | spi1 clock | smc0 data 4 notes: no notes pc_13 i/oa pupunonevdd_extdesc: pc positi on 13 | spi1 master in, slave out | smc0 data 5 notes: no notes pc_14 i/o a pu pu none vdd_ext desc: pc position 14 | spi1 master out, slave in | smc0 data 6 notes: no notes pc_15 i/oa pupunonevdd_extdesc: pc positi on 15 | spi1 slave select output 1 | smc0 data 7 | spi1 slave select input notes: no notes pd_00 i/o a pu pu none vdd_ext desc: pd position 0 | smc0 data 8 | tm0 timer 0 notes: no notes pd_01 i/o a pu pu none vdd_ext desc: pd position 1 | smc0 data 9 | tm0 timer 1 notes: no notes pd_02 i/o a pu pu none vdd_ext desc: pd position 2 | smc0 data 10 | tm0 timer 2 notes: no notes pd_03 i/o a pu pu none vdd_ext desc: pd position 3 | smc0 data 11 | tm0 timer 3 notes: no notes pd_04 i/o a pu pu none vdd_ext desc: pd position 4 | smc0 data 12 | tm0 timer 4 notes: no notes pd_05 i/o a pu pu none vdd_ext desc: pd position 5 | smc0 data 13 | tm0 timer 5 notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes preliminary technical data rev. prf | page 57 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pd_06 i/o a pu pu none vdd_ext desc: pd position 6 | smc0 data 14 | tm0 timer 6 notes: no notes pd_07 i/o a pu pu none vdd_ext desc: pd position 7 | smc0 data 15 | tm0 timer 7 notes: no notes pd_08 i/o a pu pu none vdd_ext desc: pd position 8 | smc0 address 6 | tm0 common clock notes: no notes pd_09 i/o a pu pu none vdd_ext desc: pd position 9 | smc0 address 7 | tm0 timer5 alternate capture input notes: no notes pd_10 i/o a pu pu none vdd_ext desc: pd position 10 | smc0 address 8 | tm0 timer4 alternate capture input notes: no notes pd_11 i/o a pu pu none vdd_ext desc: pd position 11 | smc0 address 9 | tm0 timer3 alternate capture input notes: no notes pd_12 i/o a pu pu none vdd_ext desc: pd posi tion 12 | smc0 address 10 | tm0 timer2 alternate capture input notes: no notes pd_13 i/o a pu pu none vdd_ext desc: pd posi tion 13 | smc0 address 11 | tm0 timer1 alternate capture input notes: no notes pd_14 i/o a pu pu none vdd_ext desc: pd position 14 | smc0 address 12 notes: no notes pd_15 i/o a pu pu none vdd_ext desc: pd position 15 | smc0 address 13 notes: no notes pe_00 i/o a pu pu none vdd_ext desc: pe posi tion 0 | smc0 address 14 | sport0 channel a clock notes: no notes pe_01 i/o a pu pu none vdd_ext desc: pe posi tion 1 | smc0 address 15 | sport0 channel a frame sync notes: no notes pe_02 i/o a pu pu none vdd_ext desc: pe posi tion 2 | smc0 address 16 | sport0 channel data 0 notes: no notes pe_03 i/o a pu pu none vdd_ext desc: pe posi tion 3 | smc0 address 17 | sport0 channel data 1 notes: no notes pe_04 i/o a pu pu none vdd_ext desc: pe position 4 | smc0 address 18 notes: no notes pe_05 i/o a pu pu none vdd_ext desc: pe position 5 | smc0 address 19 notes: no notes pe_06 i/o a pu pu none vdd_ext desc: pe position 6 | eth0 ptp clock input | smc0 address 20 notes: no notes pe_07 i/o a pu pu none vdd_ext desc: pe position 7 | eth0 ptp auxiliary trigger input | smc0 address 21 notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes rev. prf | page 58 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pe_08 i/oa pupunonevdd_extdesc: pe posi tion 8 | eth0 ptp pulse-per-second output | smc0 address 22 | cnt2 count zero marker notes: no notes pe_09 i/o a pu pu none vdd_ext desc: pe position 9 | eth0 carrier sense | smc0 address 23 | cnt2 count up and direction notes: no notes pe_10 i/o a pu pu none vdd_ext desc: pe position 10 | eth0 management channel serial data | smc0 memory select 1 | cnt2 count down and gate notes: no notes pe_11 i/o a pu pu none vdd_ext desc: pe position 11 | eth0 management channel clock | smc0 address 24 | cnt3 count zero marker notes: no notes pe_12 i/o a pu pu none vdd_ext desc: pe position 12 | eth0 transmit data 0 | cnt3 count up and direction notes: no notes pe_13 i/o a pu pu none vdd_ext desc: pe position 13 | eth0 transmit data 1 | cnt3 count down and gate notes: no notes pe_14 i/oa pupunonevdd_extdesc: pe posi tion 14 | eth0 transmit enable | cnt1 output divider a notes: no notes pe_15 i/o a pu pu none vdd_ext desc: pe position 15 | eth0 reference clock | cnt1 output divider b notes: no notes pf_00 i/o a pu pu none vdd_ext desc: pf position 0 | eth0 receive data 0 | cnt0 output divider a notes: no notes pf_01 i/o a pu pu none vdd_ext desc: pf position 1 | eth0 receive data 1 | cnt0 output divider b notes: no notes pf_02 i/o a pu pu none vdd_ext desc: pf position 2 | usb0 vbus control | embedded trace module data 3 | smc0 byte enable 1 notes: no notes pf_03 i/o a pu pu none vdd_ext desc: pf position 3 | smc0 output enable notes: no notes pf_04 i/o a pu pu none vdd_ext desc: pf position 4 | smc0 asynchronous ready notes: no notes pf_05 i/o a pu pu none vdd_ext desc: pf position 5 | smc0 address 1 notes: no notes pf_06 i/o a pu pu none vdd_ext desc: pf position 6 | smc0 address 2 notes: no notes pf_07 i/o a pu pu none vdd_ext desc: pf position 7 | smc0 address 3 notes: no notes pf_08 i/o a pu pu none vdd_ext desc: pf position 8 | smc0 address 4 notes: no notes table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes preliminary technical data rev. prf | page 59 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f pf_09 i/o a pu pu none vdd_ext desc: pf position 9 | smc0 address 5 notes: no notes pf_10 i/o a pu pu none vdd_ext desc: pf position 10 | smc0 byte enable 0 notes: no notes refcap a na none none none vdd_ana desc: output of bandgap generator filter node (see recommended bypass filter - figure 4 ) notes: no notes smc0_ams0 i/o a pu pu none vdd_ext desc: smc0 memory select 0 notes: no notes smc0_are i/o a pu pu none vdd_ext desc: smc0 read enable notes: no notes smc0_awe i/o a pu pu none vdd_ext desc: smc0 write enable notes: no notes sys_bmode0 i/o na none none none vdd_ext desc: boot mode control 0 notes: no notes sys_bmode1 i/o na none none none vdd_ext desc: boot mode control 1 notes: no notes sys_clkin i/o na none none none vdd_ext desc: clock/crystal input notes: no notes sys_clkout i/o na pu none l vdd_ext desc: processor clock output notes: no notes sys_fault i/o a none none none vdd_ext desc: complementary fault output notes: open drain, requires an external pull-up resistor sys_hwrst i/o na none none none vdd_ext desc: processor hardware reset control notes: no notes sys_nmi i/o a none none none vdd_ext desc: non-maskable interrupt notes: requires an external pull-up resistor sys_resout i/o a pu none l vdd_ext desc: reset output notes: no notes sys_xtal a na none none none vdd_ext desc: crystal output notes: leave unconnected if an oscillator is used to provide sys_clkin. ac tive during reset. twi0_scl i/o b none none none vdd_ext desc: twi0 serial clock notes: open drain, requires external pullup resistor. consult version 2.1 of the i2c specifi- cation for the proper resistor value. if twi is not used, connect to ground. twi0_sda i/o b none none none vdd_ext desc: twi0 serial data notes: en drain, requires external pullup resistor. consult version 2.1 of the i2c specifi- cation for the proper resistor value. if twi is not used, connect to ground. usb0_dm i/o d none none none vdd_ext desc: usb0 data - notes: pull low if not using usb. usb0_dp i/o d none none none vdd_ext desc: usb0 data + notes: pull low if not using usb. usb0_id i/o na none none none vdd_ext desc: usb0 otg id notes: if usb is not used, connect to ground. table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes rev. prf | page 60 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data usb0_vbus i/o e none none none vdd _ext desc: usb0 bus voltage notes: if usb is not used, pull low vdd_ana0 s na none none none na desc: analog power supply voltage 3.0v to 3.6v (see recommended bypass - figure 4 ) notes: no notes vdd_ana1 s na none none none na desc: anal og power supply voltage 3.0v to 3.6v. (see recommended bypass - figure 4 ) notes: no notes vdd_ext s na none none none na desc: external voltage domain notes: no notes vdd_int s na none none none na desc: internal voltage domain notes: no notes vdd_vreg s na none none none na desc: vreg supply voltage notes: no notes vref0 a na none none none na desc: voltage reference for adc0. default configuration is output (see recommended bypass - figure 4 ) notes: when using internal adc reference, this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. when using external adc reference, connect to externally generated reference voltage supply vref1 a na none none none na desc: voltage reference for adc1. default configuration is output (see recommended bypass - figure 4 ) notes: when using internal adc reference, this pin should never be loaded with resistive or inductive load or connected to anything but the recommended capacitor. when using external adc reference, connect to externally generated reference voltage supply vreg_base a na none none none na desc: voltage regulator base node notes: when unused, connect to gnd or pull low table 25. adsp-cm40xf designer quick reference (continued) signal name type driver type int term reset term reset drive power domain description and notes preliminary technical data rev. prf | page 61 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f specifications for information about product specifications please contact your analog devices representative. operating conditions clock related operating conditions table 27 describes the core clock, sy stem clock, and peripheral clock timing requirements. the data presented in the tables applies to all speed grades found in the pre release products except where expressly noted. figure 10 provides a graphical representation of the various cl ocks and their available multi- plier or divider values. parameter conditions min nominal max unit v dd_int digital internal supply voltage f cclk 240 mhz 1.14 1.2 1.26 v v dd_ext 1 1 must remain powered (even if the as sociated function is not used). digital external suppl y voltage 3.13 3.3 3.47 v v dd_ana 1 analog supply voltage 3.13 3.3 3.47 v v ih 2 2 parameter value applies to all input and bidirectio nal signals except twi signals and usb0 signals. high level input voltage v dd_ext = 3.47 v 2.0 v v ih_clkin 3 3 parameter applies to sys_clkin signal. high level input voltage v dd_ext = 3.47 v 2.2 v v ihtwi 4, 5 4 parameter applies to twi_sda and twi_scl. 5 twi signals are pulled up to v bustwi . see table 26 . high level input voltage v dd_ext = 3.47 v 0.7 v vbustwi v vbustwi v v il 2 low level input voltage v dd_ext = 3.13 v 0.8 v v iltwi 4 , 5 low level input voltage v dd_ext = 3.13 v 0.3 v vbustwi v t j junction temperature t ambient = tbdc to +tbdc C40 105 c table 26. twi_vsel selections and v dd_ext /v bustwi v dd_ext nominal v bustwi min v bustwi nom v bustwi max unit twi000 1 1 designs must comply with the v dd_ext and v bustwi voltages specified for the default twi_dt setting for correct jtag boundary scan operation during reset. 3.30 3.13 3.30 3.47 v twi100 3.30 4.75 5.00 5.25 v figure 10. clock relationships and divider values sys_clkin usbclk sclk cclk csel (1 - 31) ssel (1 - 31) dsel (1 - 31) oclk osel (1 - 127) pllclk msel (1 - 127) df 1 or 2 rev. prf | page 62 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table 27. clock related operating conditions parameter restriction min typ max unit f cclk core clock frequency f cclk ? f sclk 240 mhz f sclk sclk frequency 1, 2 100 mhz f usbclk usbclk frequency 3, 4 f sclk ? f usbclk 60 mhz f oclk output clock frequency 50 mhz f tck jtg_tck frequency f tck ? f sclk /2 50 mhz f sys_clkoutj sys_clkout period jitter 5, 6 1 % f sptclkprog programmed spt clock when transmitting data and frame sync 50 mhz f sptclkprog programmed spt clock when receiving data and frame sync 50 mhz f sptclkext external spt clock when transmitting data and frame sync 7, 8 f sptclkext ? f sclk 50 mhz f sptclkext external spt clock when receiving data and frame sync 7, 8 f sptclkext ? f sclk 50 mhz f spiclkprog programmed spi clock when transmitting data 7, 8 50 mhz f spiclkprog programmed spi clock when receiving data 50 mhz f spiclkext external spi clock when transmitting data 7, 8 f spiclkext ? f sclk 50 mhz f spiclkext external spi clock when receiving data 7, 8 f spiclkext ? f sclk 50 mhz f tmrclkext external tmr clock f tmrclkext ? f sclk /4 25 mhz f sinclkprog programmed sinc clock f sinclkprog ? f sclk /4 20 mhz f refclkext external ethernet mac clock f refclkext ? f sclk 50 mhz 1 supporting documents may use either sclk or sysc lk when referring to system clock frequency. 2 sclk is the clock for the system logic. do cumentation may interchangeably refer to th is clock as sysclk, e.g. for pll configura tion mmr accesses. 3 supporting documents may use either usbclk or dclk when referring to usb clock frequency. 4 usbclk is the clock for the usb peripheral . documentation may interchangeably refer to this clock as dclk, e.g. for pll configu ration mmr accesses. 5 sys_clkout jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the sys_clkin source. due to the dependency on these factors the measured jitter may be high er or lower than this specific ation for each end application. 6 the value in the typ field is the percentage of the sys_clkout period. 7 the maximum achievable frequency for any peri pheral in external clock mode is dependent on being able to meet the setup and hol d times in the ac timing specifications for that peripheral. 8 the peripheral external clock frequency must also be less than or equal to f sclk that clocks the peripheral. table 28. phase-locked loop operating conditions parameter minimum maximum unit f pllclk pll clock frequency 250 1000 mhz preliminary technical data rev. prf | page 63 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f electrical characteristics parameter test conditions min typical max unit v oh high level output voltage v dd_ext = 3.13 v, i oh = C0.5 ma 2.4 v v ol low level output voltage v dd_ext = 3.13 v, i ol = 2.0 ma 0.4 v v oltwi 1 1 applies to bidirectional pins twi_scl and twi_sda. low level output voltage v dd_ext = 3.13 v, i ol =2.0ma 0.4 v i ih 2 2 applies to input pins. high level input current v dd_ext =3.47 v, v in = 3.47 v 10 a i il 2 low level input current v dd_ext =3.47 v, v in = 0 v 10 a i ih_pd 3 3 applies to signal jtg_tck. high level input current v dd_ext = 3.47 v, v in = 3.47 v 100 a i ih_pu 4 4 applies to signal s jtg_tms, jtg_trst , and jtag_tdi. low level input current v dd_ext = 3.47 v, v in = 0 v 100 a i il_usb0 5 5 applies to signals us b0_dm and usb0_vbus. low level input current v dd_ext = 3.47 v, v in = 0 v 200 a i ozh 6 6 applies to three-statable pins. three-state leakage current v dd_ext = 3.47 v, v in = 3.47 v 10 a i ozhtwi 1 three-state leakage current v dd_ext =3.47 v, v in = tbd v 10 a i ozl 6 three-state leakage current v dd_ext = 3.47 v, v in = 0 v 10 a c in 7 7 applies to all signal pins. input capacitance f in = 1 mhz t j = 25c v in =3.3v tbd pf i dd_deepsleep 8 8 see the adsp-cm40xf mixed-signal control pr ocessor with arm cortex-m4 and 16-bit adcs hardware reference for definition of deep sleep operating mode. v dd_int current in deep sleep mode f cclk =0 mhz f sclk =0mhz tbd ma i dd_idle v dd_int current in idle f cclk = 200 mhz asf = tbd (idle) f sclk =100mhz f usbclk = 0 mhz (usb disabled) no dma activity t j = 25c tbd ma i dd_typ v dd_int current f cclk = 200 mhz asf =1.0(typical), f sclk =100mhz f usbclk = 0 mhz (usb disabled) no dma activity t j = 25c tbd ma i dd_int v dd_int current f cclk ?? 0 mhz f sclk ? 0 mhz see i ddint_tot equation ma i dd_ext v dd_ext current see i ddint_tot equation ma i dd_ana v dd_ana current tbd ma rev. prf | page 64 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data total power dissipation (pd) total power dissipation is the su m of power dissipation for each v dd domain, shown in the following equation. p d = p d_int + p d_ana + p d_ext where: p d_int = v dd_int i dd_int Cinternal voltage domain power dissipation p d_ana = v dd_ana i dd_ana C analog 3.3 v voltage domain power dissipation p d_ext = v dd_ext i dd_ext C digital 3.3 v voltage domain power dissipation total external power dissipation (idd_ext) there are three different items that contribute to the digital 3.3 v supply power dissipation: io switching, flash subsystem, and analog subsystem (digital po rtion), shown in the following equation. i ddext_tot = i ddext_io + i ddext_flash + i ddext_ana where: i ddext_io (ma) = {v ddext c l f/2 (o tr) u}C io switching current the io switching current is the sum of the switching current for all of the enabled peripherals. fo r each peripheral the capacitive load of each pin in farads (c l ), operating frequency in mhz (f), number of output pins (o), toggle ratio for each pin (tr), and peripheral utilization (u) are considered. i ddext_flash (ma) = 25 ma C maximum flash subsystem current i ddext_ana (ma) = tbd ma C analog subsystem current total processor internal power dissipation (idd_int) total internal power dissipation for the processor subsystem has two components: 1. static, including leakage current (deep sleep) 2. dynamic, due to tr ansistors switching characteristics for each clock domain many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. the following eq uation describes the internal current consumption. i ddint_tot = i ddint_cclk_dyn + i ddint_sclk_dyn + i ddint_usbclk_dyn + i ddint_dma_dr_dyn + i ddint_deepsleep i ddint_deepsleep is the only item present th at is part of the static power dissipation component. i ddint_deepsleep is specified as a function of voltage (v dd_int ) and temperature (see figure 11 ). there are five different items th at contribute to the dynamic power dissipation. thes e components fall into three broad cate- gories: application-dependent currents, clock currents, and data transmission currents. application-dependent current the application-dependent current includes the dynamic cur- rent in the core clock domain. core clock (cclk) use is subject to an activity scaling factor (asf) that represents applicatio n code running on the processor core and l1 memory ( table 29 ). the asf is combined with the cclk frequency and v dd_int dependent data in figure 12 to calculate this portion. i ddint_cclk_dyn (ma) = figure 12 asf figure 11. static current C i dd_deepsleep (ma) table 29. activity scaling factors (asf) i dd_int power vector asf i dd-peak tbd i dd-coremark (typical) 1.0 i dd-drystone tbd i dd-whetstone tbd i dd-idle tbd 60 t j (c) 0 30 50 40 20 100 i ddint_deepsleep (ma) 10 70 80 90 -40 -20 0 25 40 55 70 85 100 105 115 125 tbd preliminary technical data rev. prf | page 65 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f clock current the dynamic clock currents prov ide the total power dissipated by all transistors switching in the clock paths. the power dissi- pated by each clock domain is dependent on voltage (v dd_int ), operating frequency and a unique scaling factor. i ddint_sclk_dyn (ma) = tbd f sclk (mhz) v dd_int (v) the dynamic component of the us b clock is a unique case. the usb clock contributes a near cons tant current value when used. i ddint_usbclk_dyn (ma) = tbd ma (if usb enabled) data transmission current the data transmission current represents the power dissipated when transmitting data. this cu rrent is expressed in terms of data rate. the calculation is performed by adding the data rate (mb/s) of each dma and core dr iven access to peripherals and l2/external memory. this number is then multiplied by a coef- ficient and v dd_int . the following equation provides an estimate of all data transmission current. i ddint_dma_dr_dyn (ma) = tbd ma data rate (mb/s) v dd_int (v) figure 12. cclk dynamic current (ma, with asf = 1, v dd_int = 1.20 v) 500 f cclk (mhz) 0 200 400 300 100 i ddint_cclk_dyn (ma) 40 80 120 160 200 240 tbd rev. prf | page 66 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adc/dac specifications adc specifications typical values assume v dd_ana = 3.3 v, v ref = 2.5 v. parameter min typ max unit test conditions/comment analog input adc0_v in, 00C11 , adc1_v in, 00C11 requirement single-ended input voltage range 0 2.5 2.75 v for input voltage >2.5 v, must use external voltage reference (input mode) characteristic dc leakage current 1 a input resistance 85 ohms figure 5 on page 6 input capacitance 9.0 pf condition 1= track, figure 5 on page 6 1.5 pf condition 2 = hold, includes all parasitic capacitances, figure 5 on page 6 voltage reference (output mode) v ref0 , v ref1 characteristic output voltage 2.5 0.25% v long-term stability 150 ppm for 1000hrs output voltage thermal hysteresis 50 ppm output impedance 0.4 1.0 ohms temperature coefficient 20 ppm/c t junction = C40c to +105c voltage reference (input mode) v ref0 , v ref1 requirement input voltage range 0 2.5 2.75 v requires 750 a capable source current dc leakage current 290 a input capacitance 0.6 pf static performance dc accuracy adc0_v in, 00C11 , adc1_v in, 00C11 characteristic resolution 16 bits no missing codes, natural binary coding adsp-cm403f/ADSP-CM408F/ adsp-cm409f differential non-linearity (dnl) C0.99 +1.5 lsb figure 13 on page 69 integral non-linearity (inl) 3.5 lsb figure 16 on page 69 offset error 5.0 lsb offset error match 2 lsb channel-to-channel, within one adc offset drift 2 ppm/c gain error 25 lsb gain error match 1 lsb adsp-cm402f/adsp-cm407f differential non-linearity (dnl) C0.99 +2.0 lsb figure 13 on page 69 integral non-linearity (inl) 12.0 lsb figure 16 on page 69 offset error 12.0 lsb offset error match 2.0 lsb channel to channel, within one adc offset drift 2.0 ppm/c gain error 30 lsb preliminary technical data rev. prf | page 67 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f gain error match lsb dynamic performance throughput adc0_v in, 00C11 , adc1_v in, 00C11 conversion rate 2.63 msps acquisition time 150 ns ac accuracy adc0_v in, 00C11 , adc1_v in, 00C11 characteristic adsp-cm403f/ADSP-CM408F/ adsp-cm409f signal-to-noise ratio (snr) 1 81.25 db signal-to-(noise + distortion) ratio (sinad) 1 81 db total harmonic distortion (thd) 1 C90 db spurious-free dynamic range| (sfdr) 1 90 dbc dynamic range 82 83 db f in = dc effective number of bits (enob) 13.2 bits adsp-cm402f/adsp-cm407f signal-to-noise ratio (snr) 1 74 db signal-to-(noise + distortion) ratio (sinad) 1 73 db total harmonic distortion (thd) 1 C88 db spurious-free dynamic range (sfdr) 1 88 dbc dynamic range 75.5 db f in = dc effective number of bits (enob) 11.8 bits channel-to-channel isolation C95 db any channel pair referenced on same adc adc-to-adc isolation C100 db any channel pair referenced on opposite adc 1 f in = 1 khz, 0 v to 2.5 v input, 2.63 msps parameter min typ max unit test conditions/comment rev. prf | page 68 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data dac specifications typical values assume v dd_ana = 3.3 v, v ref = 2.5 v. parameter min typ max unit test condition analog output dac0_vout,dac1_vout characteristic output voltage range 0.1 to 2.5 v output impedance tbd ohms ohms ohms normal operation dac @ full scale dac @ zero scale update rate 50 khz short circuit current to gnd 30 ma short circuit current to v dd 30 ma static performance dc accuracy rl = 500 ohms, cl = 100 pf characteristic resolution 12 bits differential non-linearity (dnl) 0.99 lsb guaranteed monotonic integral non-linearity (inl) 2 lsb offset error 1 mv measured at code tbd gain error tbd % fsr % of full scale, measured at code 0xfff dc isolation 50 uv static output of dac0_vout while dac1_vout toggles 0 to full scale dynamic performance ac accuracy rl = 500 ohms, cl = 100 pf characteristic signal-to-noise ratio (snr) 70 db signal-to-(noise + distortion) ratio (sinad) 69 db total harmonic distortion 65 db dynamic range 68 db settling time 1.5 sec from ? to ? full scale slew rate 1.5 v/sec d/a glitch energy 8 nvCs measured when code changes from 0x7ff to 0x800 preliminary technical data rev. prf | page 69 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adc typical performance characteristics v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. figure 13. dnl vs. code figure 14. histogram of dc input at code center (external reference) figure 15. histogram of dc input at code center (internal reference) 4095 code 8192 12288 16384 positive dnl = tbd negative dnl = tbd 0 dnl (lsb) code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts code in hex 1ffc 60,000 50,000 0 40,000 30,000 1ffd 1ffe 1fff 2000 2001 2002 2003 2004 20,000 10,000 counts figure 16. inl v. code figure 17. sinad v. freuency figure 18. fft plot (internal reference) 4095 code 8192 12288 16384 positive inl = tbd negative inl = tbd 0 inl (lsb) frequency (khz) 80 85 90 95 1 10 100 1000 sinad (db) vdd_ana = tbd v vdd_ana = 3.3 v vdd_ana = tbd v 65 70 75 0 frequency (khz) 500 750 1000 0 amplitude (db) 250 1250 f s = 2.63 msps f in = 1 khz snr = tbd thd = tbd sinad = tbd rev. prf | page 70 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 19. thd vs. frequency frequency (khz) - 90 thd (db) - 95 - 100 - 105 - 110 - 85 1 10 100 1000 vdd_ana = tbd v vdd_ana = 3.3 v vdd_ana = tbd v preliminary technical data rev. prf | page 71 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f dac typical performance characteristics v dd_ana = 3.3 v, v ref = 2.5 v, t junction = 25c unless otherwise noted. figure 20. dnl vs. code figure 21. inl error and dnl error vs. temperature figure 22. zero-code error and offset error vs. temperature 0 code 500 1000 1500 0 dnl error (lsb) 2000 2500 3000 3500 4000 temperature (c) 8 6 4 2 0 - 8 - 6 - 4 - 2 error (lsb) vdd = vref = tbd v max inl max dnl min dnl min inl - 50 - 25 0 25 50 75 100 125 - 50 temperature (c) - 25 0 25 1.5 1.0 0.5 0 - 2.0 - 1.5 - 1.0 - 0.5 error (mv) 50 75 100 zero-code error 125 - 2.5 offset error figure 23. inl v. code figure 24. inl error and dnl error v. supply figure 25. inl error and dnl error v. supply 0 code 500 1000 1500 0 inl error (lsb) 2000 2500 3000 3500 4000 vdd_ana (v) 3.0 3.2 8 6 4 0 - 8 - 6 - 4 error (mv) 3.1 3.3 3.4 3.6 2.9 3.5 2 - 2 max inl max dnl min dnl min inl t j = 25c 2.9 temperature (c) 3.1 3.2 1.5 1.0 0.5 0 - 2.0 - 1.5 - 1.0 - 0.5 error (mv) 3.3 3.4 3.5 zero-code error 3.6 - 2.5 offset error 3.0 rev. prf | page 72 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data flash specifications the flash features include: ? 100,000 erase cycles per sector ? 20 years data retention flash program/erase suspend command table 30 lists parameters for the flash suspend command. flash ac characteristics and operating conditions table 31 identifies flash specific operating conditions. table 30. suspend parameters 1,2,3 parameter condition typ max units notes erase to suspend sector erase or erase resume to erase suspend 700 C s 1 program to suspend program re sume to program suspend 5 C s 1 subsector erase to suspend subsector erase or subsector erase resume to erase suspend 50 C s 1 suspend latency program 7 C s 2 suspend latency subsector erase 15 C s 2 suspend latency erase 15 C s 3 1 timing is not internally controlled. 2 any read command accepted. 3 any command except the following are accepted: sector, subsector, or bulk erase; write status register. table 31. ac characteristics and operating conditions parameter symbol min typ 1 max unit clock frequency for all commands other than read (spi-er, qio-spi protocol) f c dc C 100 mhz clock frequency for read commands f r dc C 54 mhz page program cycle time (256 bytes) 2 t pp C0.5 5 ms page program cycle time (n bytes) 2,3 t pp Cint(n/8) 0.0155 ms subsector erase cycle time t sse C0.3 1.5s sector erase cycle time t se C0.7 3 s bulk erase cycle time t be C170 250s 1 typical values given for t j = 25c. 2 when using the page program command to program consecutive bytes, optimized timing s are obtained with one sequence including al l the bytes versus several sequences of only a few bytes (1 < n < 256). 3 int(a) corresponds to the upper integer part of a. for example int(12/8) = 2, int(32/8) = 4 int(15.3) =16. preliminary technical data rev. prf | page 73 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f absolute maximum ratings stresses greater than those listed in the table may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 26 and table 33 provides details about package branding. for a complete listing of prod- uct availability, see pre release products on page 122 . parameter rating internal supply voltage (v dd_int ) C0.33 v to +1.32 v external (i/o) supply voltage (v dd_ext ) C0.33 v to +3.63 v analog supply voltage (v dd_ana ) C0.33 v to +3.63 v digital input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 32 . 2 applies only when v dd_ext is within specifications. when v dd_ext is outside speci- fications, the range is v dd_ext 0.2 volts. C0.33 v to +3.63 v twi digital input voltage 1, 2, 3 3 applies to pins twi_scl and twi_sda. C0.33 v to +5.50 v digital output voltage swing C0.33 v to v dd_ext + 0.5 v analog input voltage 4 4 applies only when v dd_ana is within specification. when v dd_ana is outside speci- fications, the range is v dd_ana 0.2 volts. C0.33 v to +3.63 v voltage reference input voltage (v ref0 , v ref1 ) 4 C0.33 v to +2.75 v usb0_dx input C0.33 v to +5.25 v usb0_vbus input voltage C0.33 v to +6.00 v i oh /i ol current per signal 1 6 ma (max) storage temperature range C65c to +150c junction temperature while biased +125 c table 32. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with th e exception of sys_clkin, sys_xtal. v in min (v) v in max (v) maximum duty cycle tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd figure 26. product information on package table 33. package brand information brand key field description adsp-cm40xf product name 1 1 see available products in pre release products on page 122 . t temperature range pp package type z rohs compliant designation cc see ordering guide vvvvvv.x assembly lot code n product revision yyww date code esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. adsp-cm40x a #yyww country_of_origin vvvvvv.x-n tppz-cc rev. prf | page 74 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data timing specifications specifications are subject to change without notice. clock and reset timing table 34 and figure 27 describe clock and reset operations. per the cclk, sclk, usbclk, and oclk timing specifications in table 27 clock related operating conditions , combinations of sys_clkin and clock multipliers mu st not select clock rates in excess of the processors maximum instruction rate. table 34. clock and reset timing parameter min max unit timing requirements f ckin sys_clkin frequency (using a crystal) 1, 2, 3 20 50 mhz f ckin sys_clkin frequency (using a crystal oscillator) 1, 2, 3 20 60 mhz t ckinl sys_clkin low pulse 1 6.67 ns t ckinh sys_clkin high pulse 1 6.67 ns t wrst sys_hwrst asserted pulse width low 4 11 t ckin ns 1 applies to pll bypass mode and pll non bypass mode. 2 the t ckin period (see figure 27 ) equals 1/f ckin . 3 if the cgu_ctl.df bit is set, the minimum f ckin specification is 40 mhz. 4 applies after power-up se quence is complete. see table 35 and figure 28 for power-up reset timing. figure 27. clock and reset timing sys_clkin t wrst t ckin t ckinl t ckinh sys_hwrst preliminary technical data rev. prf | page 75 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f power-up reset timing in figure 28 , v dd_supplies are v dd_int , v dd_ext , v dd_vreg ,v dd_ana0 , and v dd_ana1 . table 35. power-up reset timing parameter min max unit timing requirement t rst_in_pwr sys_hwrst and jtg_trst deasserted after v dd_int , v dd_ext , v dd_vreg , v dd_ana0 , v dd_ana1 , and sys_clkin are stable and within specification 11 t ckin ns figure 28. power -up reset timing t rst_in_pwr clkin v dd_supplies sys_hwrst and jtg_trst rev. prf | page 76 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data asynchronous read table 36. asynchronous memory read (bxmode = b#00) parameter min max unit timing requirements t sdatare data in setup before smc0_are high 8.2 ns t hdatare data in hold after smc0_are high 0 ns t dardyare smc0_ardy valid after smc0_are low 1, 2 (rat C 2.5) t sclk C 17.5 ns switching characteristics t addrare smc0_ax/smc0_amsx assertion before smc0_are low 3 (prest + rst + preat) t sclk C 3 ns t aoeare smc0_aoe assertion before smc0_are low (rst + preat) t sclk C 3 ns t hare output 4 hold after smc0_are high 5 rht t sclk C2 ns t ware smc0_are active low width 6 rat t sclk C 2 ns t dareardy smc0_are high delay after smc0_ardy assertion 1 2.5 t sclk 3.5 t sclk + 17.5 ns 1 smc0_bxctl.ardyen bit = 1. 2 rat value set using the smc_bxtim.rat bits. 3 prest, rst, and preat values set using the smc_bxetim.pre st bits, smc_bxtim.rst bits, and the smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams , smc0_aoe . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. figure 29. asynchronous read smc0_are smc0_amsx smc0_ax t ware smc0_aoe smc0_dx (data) smc0_ardy t aoeare t addrare t dardyare t hare t hdatare t dareardy t sdatare preliminary technical data rev. prf | page 77 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f asynchronous flash read table 37. asynchronous flash read parameter min max unit switching characteristics t amsadv smc0_ax (address)/smc0_amsx assertion before smc0_aoe low 1 prest t sclk C 2 ns t wadv smc0_aoe active low width 2 rst t sclk C 3 ns t dadvare smc0_are low delay from smc0_aoe high 3 preat t sclk C 3 ns t hare output 4 hold after smc0_are high 5 rht t sclk C 2 ns t ware 6 smc0_are active low width 7 rat t sclk C 2 ns 1 prest value set using the smc_bxetim.prest bits. 2 rst value set using th e smc_bxtim.rst bits. 3 preat value set using th e smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. 7 rat value set using the smc_bxtim.rat bits. figure 30. asynchronous flash read smc0_ax (address) t amsadv t dadvare t wadv t ware t hare read latched data smc0_amsx (nor_ce) smc0_aoe (nor_adv) smc0_are (nor_oe) smc0_dx (data) rev. prf | page 78 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data asynchronous page mode read table 38. asynchronous page mode read parameter min max unit switching characteristics t av smc0_ax (address) valid for first address min width 1 (prest + rst + preat + rat) t sclk C 2 ns t av1 smc0_ax (address) valid for subsequent smc0_ax (address) min width pgws t sclk C 2 ns t wadv smc0_aoe active low width 2 rst t sclk C 3 ns t hare output 3 hold after smc0_are high 4 rht t sclk C 2 ns t ware 5 smc0_are active low width 6 rat t sclk C 2 ns 1 prest, rst, preat and rat values set using the smc_bxetim.prest bits, smc_bxtim.rst bits, smc_bx etim.preat bits, and the smc_bx tim.rat bits. 2 rst value set using the smc_bxtim.rst bits. 3 output signals are smc0_ax, smc0_amsx . 4 rht value set using the smc_bxtim.rht bits. 5 smc_bxctl.ardyen bit = 0. 6 rat value set using the smc_bxtim.rat bits. figure 31. asynchron ous page mode read smc0_amsx (nor_ce) smc0_are (nor_oe) smc0_aoe (nor_adv) smc0_dx (data) a0 t wadv t ware t hare d0 d1 d2 d3 a0 + 1 a0 + 2 a0 + 3 t av t av1 t av1 t av1 read latched data read latched data read latched data read latched data smc0_ax (address) preliminary technical data rev. prf | page 79 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f asynchronous write table 39. asynchronous memory write (bxmode = b#00) parameter min max unit timing requirement t dardyawe 1 smc0_ardy valid after smc0_awe low 2 (wat C 2.5) t sclk C 17.5 ns switching characteristics t endat data enable after smc0_amsx assertion C3 ns t ddat data disable after smc0_amsx deassertion 3 ns t amsawe smc0_ax/smc0_amsx assertion before smc0_awe low 3 (prest + wst + preat) t sclk C 5 ns t hawe output 4 hold after smc0_awe high 5 wht t sclk C 2 ns t wawe 6 smc0_awe active low width 2 wat t sclk C 2 ns t daweardy 1 smc0_awe high delay after smc0_ardy assertion 2.5 t sclk 3.5 t sclk + 17.5 ns 1 smc_bxctl.ardyen bit = 1. 2 wat value set using the smc_bxtim.wat bits. 3 prest, wst, preat values set using the smc_bxetim.prest bits, smc_bxtim.wst bits, smc_bxetim.pre at bits, and the smc_bxtim.rat bits. 4 output signals are data, smc0_ax, smc0_amsx , smc0_abex . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. figure 32. asynchronous write smc0_awe smc0_abex smc0_ax t dardyawe t amsawe t daweardy t endat t ddat t hawe t wawe smc0_amsx smc0_dx (data) smc0_ardy rev. prf | page 80 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data asynchronous flash write all accesses table 40. asynchronous flash write parameter min max unit switching characteristics t amsadv smc0_ax/smc0_amsx assertion before smc0_aoe low 1 prest t sclk C 2 ns t dadvawe smc0_awe low delay from smc0_aoe high 2 preat t sclk C 5 ns t wadv smc0_aoe active low width 3 wst t sclk C 3 ns t hawe output 4 hold after smc0_awe high 5 wht t sclk C 2 ns t wawe 6 smc0_awe active low width 7 wat t sclk C 2 ns 1 prest value set using the smc_bxetim.prest bits. 2 preat value set using th e smc_bxetim.preat bits. 3 wst value set using the smc_bxtim.wst bits. 4 output signals are data, smc0_ax, smc0_amsx . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. 7 wat value set using the smc_bxtim.wat bits. figure 33. asynchronous flash write smc0_amsx (nor_ce ) smc0_awe (nor_we) smc0_ax (address) smc0_aoe (nor_adv) t amsadv t dadvawe smc0_dx (data) t wadv t wawe t hawe table 41. all accesses parameter min max unit switching characteristic t turn smc0_amsx inactive width (it + tt) t sclk C 2 ns preliminary technical data rev. prf | page 81 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (spt_clk) width. in figure 34 either the rising edge or the fall- ing edge of spt_clk (external or internal) can be used as the active sampling edge. when externally generated the sport clock is called f sptclkext : when internally generated, the programmed sport clock (f sptclkprog ) frequency in mhz is set by the following equation where clkdiv is a field in the sport_div register that can be set from 0 to 65535: t sptclkext 1 f sptclkext ------------------------------ - = f sptclkprog f sclk1 clkdiv 1 + ?? ------------------------------------ - = t sptclkprog 1 f sptclkprog ---------------------------------- - = table 42. serial portsexternal clock parameter min max unit timing requirements t sfse frame sync setup before spt_clk (externally generated frame sync in either transmit or receive mode) 1 2ns t hfse frame sync hold after spt_clk (externally generated frame sync in either transmit or receive mode) 1 2.7 ns t sdre receive data setup before receive spt_clk 1 2ns t hdre receive data hold after spt_clk 1 2.7 ns t sclkw spt_clk width 2 0.5 t sptclkext C 1 ns t sptclk spt_clk period 2 t sptclkext C 1 ns switching characteristics t dfse frame sync delay after spt_clk (internally generated frame sync in either transmit or receive mode) 3 14.5 ns t hofse frame sync hold after spt_clk (internally generated frame sync in either transmit or receive mode) 3 2ns t ddte transmit data delay after transmit spt_clk 3 14 ns t hdte transmit data hold after transmit spt_clk 3 2ns 1 referenced to sample edge. 2 this specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jit ter on the external spt_clk. for the external spt_clk maximum frequency, see the f sptclkext specification in table 27 clock related operating conditions . 3 referenced to drive edge. rev. prf | page 82 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table 43. serial portsinternal clock parameter min max unit timing requirements t sfsi frame sync setup before spt_clk (externally generated frame sync in either transmit or receive mode) 1 12 ns t hfsi frame sync hold after spt_clk (externally generated frame sync in either transmit or receive mode) 1 C0.5 ns t sdri receive data setup before spt_clk 1 3.4 ns t hdri receive data hold after spt_clk 1 1.5 ns switching characteristics t dfsi frame sync delay after spt_clk (internally generated frame sync in transmit or receive mode) 2 3.5 ns t hofsi frame sync hold after spt_clk (internally generated frame sync in transmit or receive mode) 2 C1 ns t ddti transmit data delay after spt_clk 2 3.5 ns t hdti transmit data hold after spt_clk 2 C1.25 ns t sclkiw spt_clk width 3 0.5 t sptclkprog C 1 ns t sptclk spt_clk period 3 t sptclkprog C 1 ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 see table 27 clock related operating conditions for details on the minimum period that may be programmed for f sptclkprog . preliminary technical data rev. prf | page 83 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f figure 34. serial ports drive edge sample edge spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) t hofsi t hfsi t hdri data receiveinternal clock drive edge sample edge t hfsi t ddti data transmitinternal clock drive edge sample edge t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsi t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) rev. prf | page 84 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table 44. serial portsenable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit spt_clk 1 1ns t ddtte data disable from external transmit spt_clk 1 14 ns t ddtin data enable from internal transmit spt_clk 1 C1 ns t ddtti data disable from internal transmit spt_clk 1 2.8 ns 1 referenced to drive edge. figure 35. serial portsenable and three-state drive edge drive edge t ddtin t ddten t ddtte spt_clk (sport clock internal) spt_a/bdx (data channel a/b) spt_clk (sport clock external) spt_a/bdx (data channel a/b) drive edge drive edge t ddtti preliminary technical data rev. prf | page 85 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f the spt_tdv output signal becomes active in sport multi- channel mode. during transmit slots (enabled with active channel selection registers) th e spt_tdv is asserted for com- munication with external devices. table 45. serial portstdv (transmit data valid) parameter min max unit switching characteristics t drdven data-valid enable delay from drive edge of external clock 1 2ns t dfdven data-valid disable delay from drive edge of external clock 1 14 ns t drdvin data-valid enable delay from drive edge of internal clock 1 C1 ns t dfdvin data-valid disable delay from drive edge of internal clock 1 3.5 ns 1 referenced to drive edge. figure 36. serial portstransmit data valid internal and external clock drive edge drive edge spt_clk (sport clock external) t drdven t dfdven drive edge drive edge spt_clk (sport clock internal) t drdvin t dfdvin spt_a/btdv spt_a/btdv rev. prf | page 86 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data table 46. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse data and data-valid enable delay from late external transmit frame sync or external receive frame sync with mce = 1, mfd = 0 1 14 ns t ddtenfs data enable for mce = 1, mfd = 0 1 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justi fied as well as standard seri al mode, and mce = 1, mfd = 0. figure 37. external late frame sync drive sample 2nd bit 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/btdv (transmit data valid) preliminary technical data rev. prf | page 87 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f serial peripheral interface (spi) portmaster timing table 47 and figure 38 describe spi port master operations. when internally generated, the programmed spi clock (f spiclkprog ) frequency in mhz is set by the following equation where baud is a field in the sp i_clk register that can be set from 0 to 65535: note that: ? in dual mode data transmit the spi_miso signal is also an output. ? in quad mode data transmit the spi_miso, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_mosi signal is also an input. ? in quad mode data receive the spi_mosi, spi_d2, and spi_d3 signals are also inputs. f spiclkprog f sclk1 baud 1 + ?? ------------------------------- = t spiclkprog 1 f spiclkprog --------------------------------- = table 47. serial peripheral interface (spi) portmaster timing parameter min max unit timing requirements t sspidm data input valid to spi_clk edge (data input setup) 3.2 ns t hspidm spi_clk sampling edge to data input invalid 1.2 ns switching characteristics t sdscim spi_sel low to first spi_clk edge for cpha = 1 1 [t sclk C 2] or [18] ns spi_sel low to first spi_clk edge for cpha = 0 1 [1.5 t sclk C 2] or [13] ns t spichm spi_clk high period 2 0.5 t spiclkprog C 1 ns t spiclm spi_clk low period 2 0.5 t spiclkprog C 1 ns t spiclk spi_clk period 2 t spiclkprog C 1 ns t hdsm last spi_clk edge to spi_sel high for cpha = 1 1 [1.5 t sclk C2] or [13] ns last spi_clk edge to spi_sel high for cpha = 0 1 [t sclk C2] or [18] ns t spitdm sequential transfer delay 1, 3 [t sclk C 1] or [19] ns t ddspidm spi_clk edge to data out valid (data out delay) 2.6 ns t hdspidm spi_clk edge to data out invalid (data out hold) C1.5 ns 1 whichever is greater. 2 see table 27 clock related operating conditions for details on the minimum period that may be programmed for t spiclkprog . 3 applies to sequential mode with stop 1. rev. prf | page 88 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 38. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spi_sel (output) spi_clk (output) data outputs (spi_mosi) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm data inputs (spi_miso) data outputs (spi_mosi) data inputs (spi_miso) rev. prf | page 89 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data serial peripheral interface (spi) portslave timing table 48 and figure 39 describe spi port slave operations. note that: ? in dual mode data transmit the spi_mosi signal is also an output. ? in quad mode data transmit the spi_mosi, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_miso signal is also an input. ? in quad mode data receive the spi_miso, spi_d2, and spi_d3 signals are also inputs. ? in spi slave mode the spi clock is supplied externally and is called f spiclkext : t spiclkext 1 f spiclkext ----------------------------- = table 48. serial peripheral interface (spi) portslave timing parameter min max unit timing requirements t spichs spi_clk high period 1 0.5 t spiclkext C 1 ns t spicls spi_clk low period 1 0.5 t spiclkext C 1 ns t spiclk spi_clk period 1 t spiclkext C 1 ns t hds last spi_clk edge to spi_ss not asserted 5 ns t spitds sequential transfer delay t spiclk C 1 ns t sdsci spi_ss assertion to first spi_clk edge 10.5 ns t sspid data input valid to spi_clk edge (data input setup) 2 ns t hspid spi_clk sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spi_ss assertion to data out active 0 14 ns t dsdhi spi_ss deassertion to data high impedance 0 12.5 ns t ddspid spi_clk edge to data out valid (data out delay) 14 ns t hdspid spi_clk edge to data out invalid (data out hold) 0 ns 1 this specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jit ter on the external spi_clk. for the external spi_clk maximum frequency see the t spiclkext specification in table 27 clock related operating conditions . rev. prf | page 90 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 39. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spi_ss (input) spi_clk (input) t hspid data outputs (spi_miso) cpha = 1 cpha = 0 data inputs (spi_mosi) data outputs (spi_miso) data inputs (spi_mosi) preliminary technical data rev. prf | page 91 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f serial peripheral interface (spi) portspi_rdy slave timing table 49. spi portspi_rdy slave timing parameter min max unit switching characteristics t dspisckrdysr spi_rdy de-assertion from last input spi_clk edge in slave mode receive 3 t sclk 4 tsclk + 10 ns t dspisckrdyst spi_rdy de-assertion from last input spi_clk edge in slave mode transmit 4 t sclk 5 tsclk + 10 ns figure 40. spi_rdy de-assertion from valid input spi_clk edge in slave mode receive (fcch = 0) figure 41. spi_rdy de-assertion fr om valid input spi_clk edge in slave mode tran smit (fcch = 1) spi_clk (cpol = 0) spi_clk (cpol = 1) t dspisckrdysr spi_rdy (o) spi_clk (cpol = 0) spi_clk (cpol = 1) cpha = 1 cpha = 0 spi_clk (cpol = 1) spi_clk (cpol = 0) t dspisckrdyst spi_rdy (o) spi_clk (cpol = 1) spi_clk (cpol = 0) cpha = 1 cpha = 0 rev. prf | page 92 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data serial peripheral interface (spi) portopen drain mode timing in figure 42 and figure 43 , the outputs can be spi_mosi spi_miso, spi_d2, and/or spi_d3 depending on the mode of operation. table 50. spi portodm master mode parameter min max unit switching characteristics t hdspiodmm spi_clk edge to high impeda nce from data out valid C1 ns t ddspiodmm spi_clk edge to data out va lid from high impedance 6 ns figure 42. odm master table 51. spi portodm slave mode parameter min max unit timing requirements t hdspiodms spi_clk edge to high impeda nce from data out valid 0 ns t ddspiodms spi_clk edge to data out va lid from high impedance 11 ns figure 43. odm slave spi_clk (cpol = 0) t hdspiodmm spi_clk (cpol = 1) t ddspiodmm t ddspiodmm t hdspiodmm output (cpha = 1) output (cpha = 0) t hdspiodms t ddspiodms t ddspiodms t hdspiodms spi_clk (cpol = 0) spi_clk (cpol = 1) output (cpha = 1) output (cpha = 0) preliminary technical data rev. prf | page 93 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f serial peripheral interface (spi) portspi_rdy master timing spi_rdy is used to provide flow control. the cpol and cpha bits are set in spi_ctl, while leadx, lagx, and stop are in spi_dly. table 52. spi portspi_rdy master timing parameter min max unit timing requirements t srdysckm0 minimum setup time for spi_rdy de-assertion in master mode before last valid spi_clk edge of valid data transfer to block subsequent transfer with cpha = 0 (2 + 2 baud 1 ) t sclk + 10 ns t srdysckm1 minimum setup time for spi_rdy de-assertion in master mode before last valid spi_clk edge of valid data transfer to block subsequent transfer with cpha = 1 (2 + 2 baud 1 ) t sclk + 10 ns switching characteristics t srdysckm time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transf er with cpha/cpol = 0 and baud = 0 (stop, lead, lag = 0) 4.5 t sclk 5.5 t sclk + 10 ns time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transf er with cpha/cpol = 1 and baud = 0 (stop, lead, lag = 0) 4 t sclk 5 t sclk + 10 ns time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transf er with cpha/cpol = 0 and baud 1 (stop, lead, lag = 0) (1 + 1.5 baud 1 ) t sclk (2 + 2.5 baud 1 ) t sclk + 10 ns time between assertion of spi_rdy by slave and first edge of spi_clk for new spi transf er with cpha/cpol = 1 and baud (stop, lead, lag = 0) (1 + 1 baud 1 ) t sclk (2 + 2 baud 1 ) t sclk + 10 ns 1 baud value set using the spi_clk.baud bit s. baud value = spi_clk.baud bits + 1. figure 44. spi_rdy setup befo re spi_clk with cpha = 0 spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm0 spi_rdy rev. prf | page 94 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 45. spi_rdy setup befo re spi_clk with cpha = 1 figure 46. spi_clk switching diagram after spi_rdy assertion, cpha = x spi_clk (cpol = 1) spi_clk (cpol = 0) t srdysckm1 spi_rdy spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm spi_rdy preliminary technical data rev. prf | page 95 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f serial peripheral interface (spi) portmemory map mode timing table 53. spi portmemory map mode timing parameter min max unit switching characteristic t zdspidm spi_clk edge to data-out high impedance C1 8 ns figure 47. spi_clk valid edge to data-out hi gh impedance in master mode with cpha = 0 figure 48. spi_clk valid edge to data-out hi gh impedance in master mode with cpha = 1 spi_clk (cpol = 0) spi_clk (cpol = 1) t zdspidm data in/out output input spi_clk (cpol = 1) spi_clk (cpol = 0) t zdspidm data in/out output input rev. prf | page 96 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data general-purpose port timing table 54 and figure 49 describe general-purpose port operations. timer cycle timing table 55 , table 56 , and figure 50 describe timer expired opera- tions. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency of (f sclk /4) mhz. the width value value is the timer period assigned in the tmx_tmrn_width register and can range from 1 to 2 32 C 1. note that when externally generated, the tmr clock is called f tmrclkext : table 54. general-purpose port timing parameter min max unit timing requirement t wfi general-purpose port pin input pulse width 2 t sclk ns figure 49. general-purpose port timing gpio input t wfi t tmrclkext 1 f tmrclkext -------------------------------- - = table 55. timer cycle timing (internal mode) parameter min max unit timing requirements t wl timer pulse width input low (measured in sclk cycles) 1 2 t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 2 t sclk ns switching characteristic t hto timer pulse width output (measured in sclk cycles) 2 t sclk width C 1.5 t sclk width + 1.5 ns 1 the minimum pulse width applies for tmx signal s in width capture an d external clock modes. 2 width refers to the value in the tmrx_width register (it can vary from 1 to 2 32 C 1). table 56. timer cycle timing (external mode) parameter min max unit timing requirements t wl timer pulse width input low (measured in ext_clk cycles) 1 2 t ext_clk ns t wh timer pulse width input high (measured in ext_clk cycles) 1 2 t ext_clk ns t ext_clk timer external clock period 2 t tmrclkext ns switching characteristic t hto timer pulse width output (measured in ext_clk cycles) 3 t ext_clk width C 1.5 t ext_clk width + 1.5 ns 1 the minimum pulse width applies for tmx signal s in width capture an d external clock modes. 2 this specification indicates the minimum instan taneous width or period that can be tole rated due to duty cy cle variation or jit ter on the external tmr_clk. for the external tmr_clk maximum frequency see the f tmrclkext specification in table 27 clock related operating conditions . 3 width refers to the value in the tmrx_width register (it can vary from 1 to 2 32 C 1). preliminary technical data rev. prf | page 97 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f up/down counter/rotary encoder timing pulse width modulator (pwm) timing table 58 and figure 52 describe pwm operations. figure 50. timer cycle timing table 57. up/down counter/rotary encoder timing parameter min max unit timing requirement t wcount up/down counter/rotary encoder input pulse width 2 t sclk ns figure 51. up/down counter/rotary encoder timing tmr output tmr input t wh , t wl t hto cnt_ud cnt_dg cnt_zm t wcount table 58. pwm timing parameter min max unit timing requirement t es external sync pulse width 2 t sclk ns switching characteristics t dodis output inactive (off) after trip input 1 15 ns t doe output delay after external sync 1, 2 2 t sclk + 5.5 5 t sclk + 14 ns 1 pwm outputs are: pwmx_ah, pwmx_al, pwmx_bh, pwmx _bl, pwmx_ch, pwmx_dh, pwmx_dl, and pwmx_cl. 2 when the external sync signal is synchronou s to the peripheral clock, it takes fewer clock cycles for the output to appear comp ared to when the external sync signal is asynchronous to the peripheral cloc k. for more information, see the adsp-cm40x microcontrolle r hardware reference . figure 52. pwm timing pwm_trip pwm_sync (as input) t es t doe output t dodis rev. prf | page 98 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data pulse width modulator (pwm) heightened-precision mode timing table 59 and table 60 and figure 53 and figure 54 describe heightened-precision pwm operations. table 59. pwmheightened-precision mode, output pulse parameter min max unit switching characteristics t hpwmw hp-pwm output pulse width 1 (n + m 0.25) t sclk C tbd (n + m 0.25) t sclk + tbd ns 1 n is the duty bit field (coarse duty) from the duty register. m is the enhdiv (enhanced precision divider bits) value from the hp duty register. figure 53. pwm heightened-precision mode timing, output pulse table 60. pwmheightened-precision mode, output skew parameter min max unit switching characteristics t hpwms hp-pwm output skew 1 tbd tbd ps 1 output edge difference between any two pwm channels (ah, al, bh , bl, ch, cl, dh and dl) in th e same pwm unit (a unit is pwmx wh ere x = 0, 1, 2), with the same heightened-precision edge placement. figure 54. pwm heightened-precision mode timing, output skew pwmoutput t hpwmw pwm outputs pwm outputs t hpwms preliminary technical data rev. prf | page 99 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-cm40xf mixed-signal control processor with arm cortex-m4 and 16-bit adcs hardware reference . can interface the can interface timing is described in the adsp-cm40xf mixed-signal control processor with arm cortex-m4 and 16-bit adcs hardware reference . universal serial bus (usb) on-the-goreceive and transmit timing the usb interface timing is described in the adsp-cm40xf mixed-signal control processor with arm cortex-m4 and 16-bit adcs hardware reference . rev. prf | page 100 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data 10/100 ethernet mac controller timing table 61 through table 63 and figure 55 through figure 57 describe the 10/100 ethernet mac cont roller operations. note the externally generated ethernet mac clock is called f refclkext : t refclkext 1 f refclkext ------------------------------- = table 61. 10/100 ethernet mac controller timing: rmii receive signal parameter 1 min max unit timing requirements t refclk ethx_refclk period 2 t refclkext + 50 ppm ns t refclkw ethx_refclk width 2 t refclkext 35% t refclkext 65% ns t refclkis rx input valid to rmii ethx_refclk rising edge (data in setup) 4 ns t refclkih rmii ethx_refclk rising edge to rx input invalid (data in hold) 2.0 ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. 2 this specification indicates the minimum inst antaneous width or period that can be tole rated due to duty cycle variation or jit ter on the external ref_clk. for the external ref_clk maximum frequency see the t refclkext specification in table 27 clock related operating conditions . figure 55. 10/100 ethernet mac controller timing: rmii receive signal table 62. 10/100 ethernet mac controller timing: rmii transmit signal parameter 1 min max unit switching characteristics t refclkov rmii ethx_refclk rising edge to transmit output valid (data out valid) 14 ns t refclkoh rmii ethx_refclk rising edge to tran smit output invalid (data out hold) 2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. figure 56. 10/100 ethernet mac controller timing: rmii transmit signal t refclkis t refclkih ethx_rxd1C0 ethx_crs ethx_rxerr rmii_ref_clk t refclkw t refclk t refclkov t refclkoh rmii_ref_clk ethx_txd1C0 ethx_txen t refclk preliminary technical data rev. prf | page 101 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f table 63. 10/100 ethernet mac controller timing: rmii station management parameter 1 min max unit timing requirements t mdios ethx_mdio input valid to ethx_m dc rising edge (setup) 14 ns t mdcih ethx_mdc rising edge to ethx_mdio input invalid (hold) 0 ns switching characteristics t mdcov ethx_mdc falling edge to ethx_mdio output valid t sclk + 5 ns t mdcoh ethx_mdc falling edge to ethx_mdio output invalid (hold) t sclk C2.5 ns 1 ethx_mdc/ethx_mdio is a 2-wire se rial bidirectional port for cont rolling one or more external phys. ethx_mdc is an output clock whose minimum period is programmable as a multiple of the system cloc k sclk. ethx_mdio is a bi directional data line. figure 57. 10/100 ethernet mac contro ller timing: rmii station management ethx_mdio (input) ethx_mdio (output) ethx_mdc (output) t mdios t mdcoh t mdcih t mdcov rev. prf | page 102 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data sinc timing the programmed sinc clock (f sinclkprog ) frequency in mhz is set by the following equation wh ere mdiv is a fi eld in the clk control register that can be set from 4 to 63: f sinclkprog f sclk mdiv --------------- - = t sinclkprog 1 f sinclkprog ---------------------------------- = table 64. sinc timing parameter min max unit timing requirements t ssinc sinc0_dx setup before sinc0_clkx rise 9 ns t hsinc sinc0_dx hold after sinc0_clkx rise 0 ns switching characteristics t sinclk sinc0_clkx period 1 t sinclkprog C 2.5 ns t sinclkw sinc0_clkx width 1 0.5 t sinclkprog C 2.5 ns 1 see table 27 clock related operating conditions for details on the minimum period that may be programmed for t sinclkprog . figure 58. sinc timing sinc0_clkx sinc_dx t sinclk t sinclkw t sinclkw t ssinc t hsinc preliminary technical data rev. prf | page 103 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f trace timing swd timing table 65. trace timing parameter min max unit switching characteristics t ddtrace data delay after trace_clk 0.5 t sclk + 2 ns t hdtrace data hold after trace_clk 0.5 t sclk C 2 ns figure 59. trace timing table 66. swd timing parameter min max unit timing requirements t swclk swclk period 20 ns t sswdio swdio setup before swclk high 4 ns t hswdio swdio hold after swclk high 4 ns switching characteristics t dswdio swdio delay after swclk high 12.5 ns t hoswdio swdio hold after swclk high 3.5 ns figure 60. swd timing trace_clk trace_dx t ddtrace t hdtrace swclk swdio in t swclk t sswdio t hswdio t dswdio t hoswdio swdio out rev. prf | page 104 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data jtag test and emulation port timing table 67 and figure 61 describe jtag port operations. table 67. jtag port timing parameter min max unit timing requirements t tck jtg_tck period 20 ns t stap jtg_tdi, jtg_tms setup before jtg_tck high 4 ns t htap jtg_tdi, jtg_tms hold after jtg_tck high 4 ns t ssys system inputs setup before jtg_tck high 1 12 ns t hsys system inputs hold after jtg_tck high 1 5ns t trstw jtg_trst pulse width (measured in jtg_tck cycles) 2 4tck switching characteristics t dtdo jtg_tdo delay from jtg_tck low 13.5 ns t dsys system outputs delay after jtg_tck low 3 17 ns 1 system inputs = pa_15C0, pb_15C0, pc_15C0, pd _15C0, pe_15C0, pf_10C0, sys_bmode0C1, sys_hwrst , sys_fault , sys_nmi , twi0_scl, twi0_sda, usb_id. 2 50 mhz maximum. 3 system outputs = pa_15C0, pb_15C0, pc_15C0, pd_15C0, pe_15C0, pf_10C0, smc0_ams0 , smc0_are , smc0_awe , sys_clkout, sys_fault , sys_resout . figure 61. jtag port timing jtg_tck jtg_tms jtg_tdi jtg_tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys preliminary technical data rev. prf | page 105 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f processor test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 62 shows the measurement point fo r ac measurements (except output enable/disable). the measurement point v meas is v ddext /2 for v ddext (nominal) = 3.3 v. output enable time measurement output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 63 . if multiple pins are enabled, the measurement value is that of the first pin to start driving. output disable time measurement output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the interval from when a reference signal reaches a high or low volt- age level to the point when the ou tput stops driving as shown on the left side of figure 63 . output drive currents figure 64 and figure 65 show typical current-voltage character- istics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. capacitive loading output delay, hold, enable, and disable times are based on stan- dard capacitive loads of an average of 6 pf on all pins (see figure 66 ). v load is equal to (v dd_ext )/2. figure 62. voltage reference levels for ac measurements (except output enable/disable) figure 63. output enable/disable input or output v meas v meas reference signal t dis output starts driving high impedance state output stops driving t ena figre 64. drier tpe a crrent figre 65. drier tpe b crrent 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 50 30 20 C 50 C 30 C 10 4.0 v ddext = 3.47v @ C 40 c v ddext = 3.3v @ 25 c C 20 C 40 10 40 v ddext = 3.135v @ 105 c v oh v ol C 25 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 C 5 C 10 C 50 C 30 4.0 v ddext = 3.47v @ C 40 c v ddext = 3.3v @ 25 c C 35 C 45 C 15 v ddext = 1.135@ 125 c C 20 C 40 rev. prf | page 106 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data the graph of figure 67 shows how output rise and fall times vary with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) measured by customer at top center of package. ? jt = from table 68 , table 69 , and table 70 p d = power dissipation (see total power dissipation (pd) on page 64 for the method to calculate p d ) figure 66. equivalent device loading for ac measurements (includes all fixtures) figure 67. driver type a typical rise and fall times (10%-90%) vs. load capacitance t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output load capacitance (pf) 20 0 25 15 5 10 rise and fall times (ns) 0 160 120 20 60 100 30 t fall = 3.3v @ 25 c t rise = 3.3v @ 25 c 40 80 140 t fall t rise table 68. thermal characteristics (120-lead lqfp) parameter condition typical unit ? ja 0 linear m/s air flow 21.5 c/w ? ja 1 linear m/s air flow 19.2 c/w ? ja 2 linear m/s air flow 18.4 c/w ? jc 9.29 c/w ? jt 0 linear m/s air flow 0.25 c/w ? jt 1 linear m/s air flow 0.40 c/w ? jt 2 linear m/s air flow 0.56 c/w table 69. thermal characteristics (176-lead lqfp) parameter condition typical unit ? ja 0 linear m/s air flow 21.5 c/w ? ja 1 linear m/s air flow 19.3 c/w ? ja 2 linear m/s air flow 18.5 c/w ? jc 9.24 c/w ? jt 0 linear m/s air flow 0.25 c/w ? jt 1 linear m/s air flow 0.37 c/w ? jt 2 linear m/s air flow 0.48 c/w table 70. thermal characteristics (212-ball bga) parameter condition typical unit ? ja 0 linear m/s air flow 30.0 c/w ? ja 1 linear m/s air flow 27.5 c/w ? ja 2 linear m/s air flow 26.5 c/w ? jc 9.2 c/w ? jt 0 linear m/s air flow 0.15 c/w ? jt 1 linear m/s air flow 0.24 c/w ? jt 2 linear m/s air flow 0.27 c/w t j t case ? jt p d ? ?? + = preliminary technical data rev. prf | page 107 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f values of ? ja are provided for packag e comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of ? jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. in table 68 and table 69 , airflow measurements comply with jedec standards jesd51-2 and jesd51-6. the junction-to- case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. t j t a ? ja p d ? ?? + = rev. prf | page 108 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data adsp-cm402f/adsp-cm403f 120- lead lqfp lead assignments table 71 lists the 120-lead lqfp package by lead number and table 72 lists the 120-lead lqfp package by pin name. table 71. adsp-cm402f/adsp-cm403f120-lead lqfp l ead assignments (numerical by lead number) lead no. pin name lead no. pin name lead no. pin name lead no. pin name 1 pa_13 32 jtg_trst 63 adc1_vin05 94 dac0_vout 2 vdd_ext 33 jtg_tdo/swo 64 adc1_vin06 95 vdd_ext 3 pa_12 34 jtg_tms/swdio 65 adc1_vin07 96 vdd_int 4 pa_11 35 pc_07 66 adc1_vin08 97 vdd_ext 5 pa_10 36 vdd_ext 67 adc1_vin09 98 gnd 6 pa_09 37 pc_06 68 adc1_vin10 99 sys_nmi 7 pa_08 38 pc_05 69 adc1_vin11 100 vdd_ext 8 pa_07 39 pc_04 70 vdd_ana1 101 vdd_ext 9 vdd_ext 40 pc_03 71 gnd_ana1 102 pb_10 10 pa_06 41 pc_02 72 byp_a1 103 pb_08 11 pa_05 42 pc_01 73 vref1 104 pb_09 12 pa_04 43 vdd_ext 74 gnd_vref1 105 pb_06 13 pa_03 44 vdd_int 75 refcap 106 pb_07 14 pa_02 45 pc_00 76 gnd_vref0 107 pb_05 15 pa_01 46 pb_14 77 vref0 108 vdd_int 16 vdd_int 47 pb_15 78 byp_a0 109 vdd_ext 17 vdd_ext 48 pb_13 79 gnd_ana0 110 pb_04 18 sys_resout 49 vdd_ext 80 vdd_ana0 111 pb_03 19 pa_00 50 pb_11 81 adc0_vin11 112 pb_02 20 sys_fault 51 pb_12 82 adc0_vin10 113 pb_01 21 sys_hwrst 52 gnd 83 adc0_vin09 114 pb_00 22 vdd_ext 53 vdd_ext 84 adc0_vin08 115 pa_15 23 sys_xtal 54 vdd_int 85 adc0_vin07 116 vdd_ext 24 sys_clkin 55 byp_d0 86 adc0_vin06 117 pa_14 25 vreg_base 56 dac1_vout 87 adc0_vin05 118 sys_clkout 26 vdd_vreg 57 adc1_vin00 88 adc0_vin04 119 sys_bmode1 27 vdd_ext 58 adc1_vin01 89 adc0_vin03 120 sys_bmode0 28 twi0_scl 59 adc1_vin02 90 gnd_ana2 121 gnd 29 twi0_sda 60 adc1_vin03 91 adc0_vin02 30 jtg_tdi 61 gnd_ana3 92 adc0_vin01 31 jtg_tck/swclk 62 adc1_vin04 93 adc0_vin00 * pin no. 121 is the gnd supply (see figure 69 ) for the processor; this pad must connect to gnd. preliminary technical data rev. prf | page 109 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f table 72. adsp-cm402f/adsp-cm403f 120-lead lqfp lead assignments (alphabetical by pin name) pin name lead no. pin name lead no. pin name lead no. pin name lead no. adc0_vin00 93 gnd 121 pb_03 111 twi0_scl 28 adc0_vin01 92 gnd_ana0 79 pb_04 110 twi0_sda 29 adc0_vin02 91 gnd_ana1 71 pb_05 107 vdd_ana0 80 adc0_vin03 89 gnd_ana2 90 pb_06 105 vdd_ana1 70 adc0_vin04 88 gnd_ana3 61 pb_07 106 vdd_ext 2 adc0_vin05 87 gnd_vref0 76 pb_08 103 vdd_ext 9 adc0_vin06 86 gnd_vref1 74 pb_09 104 vdd_ext 17 adc0_vin07 85 jtg_tck/swclk 31 pb_10 102 vdd_ext 22 adc0_vin08 84 jtg_tdi 30 pb_11 50 vdd_ext 27 adc0_vin09 83 jtg_tdo/swo 33 pb_12 51 vdd_ext 36 adc0_vin10 82 jtg_tms/swdio 34 pb_13 48 vdd_ext 43 adc0_vin11 81 jtg_trst 32 pb_14 46 vdd_ext 49 adc1_vin00 57 pa_00 19 pb_15 47 vdd_ext 53 adc1_vin01 58 pa_01 15 pc_00 45 vdd_ext 95 adc1_vin02 59 pa_02 14 pc_01 42 vdd_ext 97 adc1_vin03 60 pa_03 13 pc_02 41 vdd_ext 100 adc1_vin04 62 pa_04 12 pc_03 40 vdd_ext 101 adc1_vin05 63 pa_05 11 pc_04 39 vdd_ext 109 adc1_vin06 64 pa_06 10 pc_05 38 vdd_ext 116 adc1_vin07 65 pa_07 8 pc_06 37 vdd_int 16 adc1_vin08 66 pa_08 7 pc_07 35 vdd_int 44 adc1_vin09 67 pa_09 6 refcap 75 vdd_int 54 adc1_vin10 68 pa_10 5 sys_bmode0 120 vdd_int 96 adc1_vin11 69 pa_11 4 sys_bmode1 119 vdd_int 108 byp_a0 78 pa_12 3 sys_clkin 24 vdd_vreg 26 byp_a1 72 pa_13 1 sys_clkout 118 vref0 77 byp_d0 55 pa_14 117 sys_fault 20 vref1 73 dac0_vout 94 pa_15 115 sys_hwrst 21 vreg_base 25 dac1_vout 56 pb_00 114 sys_nmi 99 gnd 52 pb_01 113 sys_resout 18 gnd 98 pb_02 112 sys_xtal 23 * pin no. 121 is the gnd supply (see figure 69 ) for the processor; this pad must connect to gnd. rev. prf | page 110 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 68 shows the top view of the 120-lead lqfp package lead configuration and figure 69 shows the bottom view of the 120- lead lqfp package lead configuration. figure 68. 120-lead lqfp configuration (top view) figure 69. 120-lead lqfp configuration (bottom view) lead 1 lead 3 0 lead 90 lead 61 lead 120 lead 91 lead 3 1lead 60 lead 1 120-lead lqfp top view indicator lead 3 0 lead 1 lead 61 lead 90 lead 3 1 lead 60 lead 120 120-lead lqfp bottom view lead 91 gnd pad (lead 121) preliminary technical data rev. prf | page 111 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm407f/ADSP-CM408F 176- lead lqfp lead assignments table 73 lists the 176-lead lqfp package by lead number and table 74 lists the 176-lead lqfp package by pin name. table 73. adsp-cm407f/ADSP-CM408F 176-lead lqfp l ead assignments (numerical by lead number) lead no. pin name lead no. pin name lead no. pin name lead no. pin name 1 pa_13 46 jtg_trst 91 pe_05 136 vdd_ext 2 vdd_ext 47 jtg_tdo/swo 92 pe_04 137 vdd_ext 3 pa_12 48 jtg_tms/swdio 93 vdd_ext 138 pd_12 4 pa_11 49 pc_07 94 vdd_int 139 pd_13 5 pc_15 50 vdd_ext 95 byp_d0 140 pd_10 6 pa_10 51 pc_05 96 gnd_ana3 141 pd_11 7 pc_14 52 pc_06 97 adc1_vin00 142 pd_08 8 vdd_ext 53 pf_10 98 adc1_vin01 143 pd_09 9 pc_13 54 pc_04 99 adc1_vin02 144 vdd_ext 10 pc_11 55 pf_08 100 adc1_vin03 145 pd_07 11 pc_12 56 pf_09 101 adc1_vin04 146 pd_06 12 pa_09 57 vdd_ext 102 adc1_vin05 147 smc0_ams0 13 pa_08 58 pf_06 103 adc1_vin06 148 smc0_awe 14 pa_07 59 pf_07 104 adc1_vin07 149 smc0_are 15 vdd_ext 60 pc_03 105 vdd_ana1 150 vdd_ext 16 pa_06 61 pf_05 106 gnd_ana1 151 pb_10 17 pa_05 62 pc_01 107 byp_a1 152 pb_09 18 pa_04 63 pc_02 108 vref1 153 pb_08 19 pa_03 64 vdd_ext 109 gnd_vref1 154 pb_07 20 pa_02 65 vdd_int 110 refcap 155 pb_06 21 pa_01 66 pc_00 111 gnd_vref0 156 pb_05 22 vdd_int 67 pf_04 112 vref0 157 vdd_int 23 vdd_ext 68 pf_03 113 byp_a0 158 vdd_ext 24 sys_resout 69 pf_02 114 gnd_ana0 159 pb_03 25 pa_00 70 pf_01 115 vdd_ana0 160 pb_04 26 sys_fault 71 pf_00 116 adc0_vin07 161 pd_05 27 sys_hwrst 72 vdd_ext 117 adc0_vin06 162 pb_02 28 vdd_ext 73 pe_15 118 adc0_vin05 163 pd_03 29 sys_xtal 74 pe_14 119 adc0_vin04 164 pd_04 * pin no. 177 is the gnd supply (see figure 71 ) for the processor; this pad must connect to gnd. rev. prf | page 112 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data 30 sys_clkin 75 pe_13 120 adc0_vin03 165 vdd_ext 31 vreg_base 76 pb_14 121 adc0_vin02 166 pd_01 32 vdd_vreg 77 pb_15 122 adc0_vin01 167 pd_02 33 vdd_ext 78 pb_13 123 a dc0_vin00 168 pb_01 34 usb0_dm 79 vdd_ext 124 gnd_ana2 169 pd_00 35 usb0_dp 80 pb_11 125 vdd_ext 170 pa_15 36 usb0_vbus 81 pb_12 126 pe_03 171 pb_00 37 usb0_id 82 pe_12 127 pe_02 172 vdd_ext 38 pc_10 83 gnd 128 vdd_int 173 pa_14 39 pc_08 84 pe_11 129 vdd_ext 174 sys_clkout 40 pc_09 85 pe_10 130 pe_01 175 sys_bmode1 41 vdd_ext 86 vdd_ext 131 gnd 176 sys_bmode0 42 twi0_scl 87 pe_09 132 sys_nmi 177 gnd 43 twi0_sda 88 pe_08 133 pe_00 44 jtg_tdi 89 pe_07 134 pd_15 45 jtg_tck/swclk 90 pe_06 135 pd_14 table 73. adsp-cm407f/ADSP-CM408F 176-lead lqfp lead assi gnments (numerical by lead number) (continued) lead no. pin name lead no. pin name lead no. pin name lead no. pin name * pin no. 177 is the gnd supply (see figure 71 ) for the processor; this pad must connect to gnd. table 74. adsp-cm407f/ADSP-CM408F 176-lead lqfp lead assignments (alphabetical by pin name) pin name lead no. pin name lead no. pin name lead no. pin name lead no. adc0_vin00 123 pa_12 3 pd_09 143 sys_resout 24 adc0_vin01 122 pa_13 1 pd_10 140 sys_xtal 29 adc0_vin02 121 pa_14 173 pd_11 141 twi0_scl 42 adc0_vin03 120 pa_15 170 pd_12 138 twi0_sda 43 adc0_vin04 119 pb_00 171 pd_13 139 usb0_dm 34 adc0_vin05 118 pb_01 168 pd_14 135 usb0_dp 35 adc0_vin06 117 pb_02 162 pd_15 134 usb0_id 37 adc0_vin07 116 pb_03 159 pe_00 133 usb0_vbus 36 adc1_vin00 97 pb_04 160 pe_01 130 vdd_ana0 115 adc1_vin01 98 pb_05 156 pe_02 127 vdd_ana1 105 adc1_vin02 99 pb_06 155 pe_03 126 vdd_ext 2 adc1_vin03 100 pb_07 154 pe_04 92 vdd_ext 8 adc1_vin04 101 pb_08 153 pe_05 91 vdd_ext 15 adc1_vin05 102 pb_09 152 pe_06 90 vdd_ext 23 adc1_vin06 103 pb_10 151 pe_07 89 vdd_ext 28 adc1_vin07 104 pb_11 80 pe_08 88 vdd_ext 33 byp_a0 113 pb_12 81 pe_09 87 vdd_ext 41 byp_a1 107 pb_13 78 pe_10 85 vdd_ext 50 byp_d0 95 pb_14 76 pe_11 84 vdd_ext 57 gnd 83 pb_15 77 pe_12 82 vdd_ext 64 gnd 131 pc_00 66 pe_13 75 vdd_ext 72 gnd 177 pc_01 62 pe_14 74 vdd_ext 79 gnd_ana0 114 pc_02 63 pe_15 73 vdd_ext 86 gnd_ana1 106 pc_03 60 pf_00 71 vdd_ext 93 * pin no. 177 is the gnd supply (see figure 71 ) for the processor; this pad must connect to gnd. preliminary technical data rev. prf | page 113 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f gnd_ana2 124 pc_04 54 pf_01 70 vdd_ext 125 gnd_ana3 96 pc_05 51 pf_02 69 vdd_ext 129 gnd_vref0 111 pc_06 52 pf_03 68 vdd_ext 136 gnd_vref1 109 pc_07 49 pf_04 67 vdd_ext 137 jtg_tck/swclk 45 pc_08 39 pf_05 61 vdd_ext 144 jtg_tdi 44pc_09 40pf_06 58vdd_ext 150 jtg_tdo/swo47pc_10 38pf_07 59vdd_ext 158 jtg_tms/swdio 48 pc_11 10 pf_08 55 vdd_ext 165 jtg_trst 46 pc_12 11 pf_09 56 vdd_ext 172 pa_00 25 pc_13 9 pf_10 53 vdd_int 22 pa_01 21 pc_14 7 refcap 110 vdd_int 65 pa_02 20 pc_15 5 smc0_ams0 147 vdd_int 94 pa_03 19 pd_00 169 smc0_are 149 vdd_int 128 pa_04 18 pd_01 166 smc0_awe 148 vdd_int 157 pa_05 17 pd_02 167 sys_bmode0 176 vdd_vreg 32 pa_06 16 pd_03 163 sys_bmode1 175 vref0 112 pa_07 14 pd_04 164 sys_clkin 30 vref1 108 pa_08 13 pd_05 161 sys_clkout 174 vreg_base 31 pa_09 12 pd_06 146 sys_fault 26 pa_10 6 pd_07 145 sys_hwrst 27 pa_11 4 pd_08 142 sys_nmi 132 table 74. adsp-cm407f/ADSP-CM408F 176-lead lqfp lead assignments (alphabetical by pin name) (continued) pin name lead no. pin name lead no. pin name lead no. pin name lead no. * pin no. 177 is the gnd supply (see figure 71 ) for the processor; this pad must connect to gnd. rev. prf | page 114 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 70 shows the top view of the 176-lead lqfp lead config- uration and figure 71 shows the bottom vi ew of the 176-lead lqfp lead configuration. figure 70. 176-lead lqfp lead configuration (top view) lead 1 lead 44 lead 1 3 2 lead 8 9 lead 176 lead 1 33 lead 45 lead 88 lead 1 indicator 176-lead lqfp top view figre 71. 176-lead lqfp lead configration (bottom vie) lead 1 3 2 lead 8 9 lead 1 lead 44 lead 1 33 lead 176 lead 88 lead 45 176-lead lqfp bottom view gnd pad (lead 177) preliminary technical data rev. prf | page 115 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f adsp-cm409f 212-ball bga ball assignments table 75 lists the 212-ball bga package by ball number and table 76 lists the 212-ball bga package by ball name. table 75. adsp-cm409f 212-ball bga ball assignments (numerical by ball number) ball no. ball name ball no. ball name ball no. ball name ball no. ball name a01 gnd d01 pa_10 k03 vreg_base t05 vdd_ext a02 pa_14 d02 pa_11 k07 gnd t06 pf_06 a03 pb_00 d03 pa_13 k08 gnd t07 pf_05 a04 pd_00 d07 vdd_int k09 gnd t08 pc_01 a05 pd_02 d08 vdd_ext k11 gnd_ana t09 pf_02 a06 pd_03 d09 vdd_ext k12 gnd_ana t10 pe_15 a07 pb_03 d10 vdd_ext k16 refcap t11 pb_15 a08 pb_06 d11 vdd_ext k17 gnd_ana t12 pb_11 a09 pb_09 d12 vdd_int k18 vdd_ana1 t13 pe_11 a10 smc0_ams0 d16 dac0_vout l01 sys_fault t14 vdd_ext a11 smc0_awe d17 adc0_vin03 l02 sys_resout t15 vdd_ext a12 pd_08 d18 adc0_vin04 l03 vdd_ext t16 gnd_ana a13 pd_10 e01 pc_14 l07 gnd t17 adc1_vin01 a14 pd_14 e02 pc_13 l08 gnd t18 adc1_vin03 a15 pe_00 e03 pa_12 l09 gnd u01 jtg_trst a16 pe_02 e16 byp_a0 l11 gnd_ana u02 gnd a17 pe_03 e17 adc0_vin05 l12 gnd_ana u03 jtg_tdo/swo a18 gnd_ana e18 adc0_vin06 l16 vref1 u04 pc_05 b01 sys_bmode1 f01 pa_09 l17 adc1_vin11 u05 pf_10 b02 gnd f02 pc_12 l18 gnd_ana u06 pf_09 b03 sys_clkout f03 pc_11 m01 sys_xtal u07 pc_03 b04 pa_15 f16 gnd_ana m02 sys_clkin u08 pc_02 b05 pb_01 f17 adc0_vin0 7 m03 pa_00 u09 pf_03 b06 pd_04 f18 adc0_vin08 m16 gnd_vref1 u10 pf_00 b07 pb_02 g01 pa_07 m17 adc1_vin10 u11 pe_14 b08 pb_05 g02 pa_06 m18 adc1_vin09 u12 pb_13 b09 pb_08 g03 pa_08 n01 usb0_dm u13 pb_12 b10 smc0_are g16 gnd_vref0 n02 usb0_vbus u14 pe_09 b11 pd_07 g17 adc0_vin10 n03 pc_10 u15 pe_08 b12 pd_11 g18 adc0_vin09 n16 gnd_ana u16 pe_06 b13 pd_12 h01 pa_05 n17 a dc1_vin07 u17 gnd_ana b14 pd_15 h02 pa_04 n18 adc1_vin08 u18 adc1_vin00 b15 sys_nmi h03 vdd_int p01 usb0_dp v01 gnd b16 pe_01 h07 gnd p02 usb0_id v02 jtg_tms/swdio b17 gnd_ana h08 gnd p03 pc_08 v03 pc_07 b18 adc0_vin00 h09 gnd p16 byp_a1 v04 pc_06 c01 pc_15 h11 gnd_ana p17 adc1_vin05 v05 pc_04 c02 sys_bmode0 h12 gnd_ana p18 adc1_vin06 v06 pf_08 c03 gnd h16 vref0 r01 twi0_sda v07 pf_07 c04 vdd_ext h17 adc0_vin11 r02 twi0_scl v08 pc_00 c05 vdd_ext h18 gnd_ana r03 pc_09 v09 pf_04 c06 pd_01 j01 pa_03 r07 vdd_ext v10 pf_01 rev. prf | page 116 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data c07 pd_05 j02 pa_02 r08 vdd_int v11 pe_13 c08 pb_04 j03 vdd_vreg r09 vdd_ext v12 pb_14 c09 pb_07 j07 gnd r10 vdd_int v13 pe_12 c10 pb_10 j08 gnd r11 gnd v14 pe_10 c11 pd_06 j09 gnd r12 byp_d0 v15 pe_07 c12 pd_09 j11 gnd_ana r16 dac1_vout v16 pe_05 c13 pd_13 j12 gnd_ana r17 adc1_vin02 v17 pe_04 c14 gnd j16 gnd_ana r18 adc1_vin04 v18 gnd_ana c15 vdd_ext j17 gnd_ana t01 jtg_tdi c16 gnd_ana j18 vdd_ana0 t02 jtg_tck/swclk c17 adc0_vin01 k01 pa_01 t03 gnd c18 adc0_vin02 k02 sys_hwrst t04 vdd_ext table 75. adsp-cm409f 212-ball bga ball assignmen ts (numerical by ball number) (continued) ball no. ball name ball no. ball name ball no. ball name ball no. ball name table 76. adsp-cm409f 212-ball bga ball assignments (alphabetical by ball name) ball name ball no. ball name ball no. ball name ball no. ball name ball no. adc0_vin00 b18 gnd_ana h12 pb_15 t11 pf_05 t07 adc0_vin01 c17 gnd_ana h18 pc_00 v08 pf_06 t06 adc0_vin02 c18 gnd_ana j11 pc_01 t08 pf_07 v07 adc0_vin03 d17 gnd_ana j12 pc_02 u08 pf_08 v06 adc0_vin04 d18 gnd_ana j16 pc_03 u07 pf_09 u06 adc0_vin05 e17 gnd_ana j17 pc_04 v05 pf_10 u05 adc0_vin06 e18 gnd_ana k11 pc_05 u04 refcap k16 adc0_vin07 f17 gnd_ana k12 pc_06 v04 smc0_ams0 a10 adc0_vin08 f18 gnd_ana k17 pc_07 v03 smc0_are b10 adc0_vin09 g18 gnd_ana l11 pc_08 p03 smc0_awe a11 adc0_vin10 g17 gnd_ana l12 pc_09 r03 sys_bmode0 c02 adc0_vin11 h17 gnd_ana l18 pc_10 n03 sys_bmode1 b01 adc1_vin00 u18 gnd_ana n16 pc_11 f03 sys_clkin m02 adc1_vin01 t17 gnd_ana t16 pc_12 f02 sys_clkout b03 adc1_vin02 r17 gnd_ana u17 pc_13 e02 sys_fault l01 adc1_vin03 t18 gnd_ana v18 pc_14 e01 sys_hwrst k02 adc1_vin04 r18 gnd_vref0 g16 pc_15 c01 sys_nmi b15 adc1_vin05 p17 gnd_vref1 m16 pd_00 a04 sys_resout l02 adc1_vin06 p18 jtg_tck/swclk t02 pd_01 c06 sys_xtal m01 adc1_vin07 n17 jtg_tdi t01 pd_02 a05 twi0_scl r02 adc1_vin08 n18 jtg_tdo/swo u03 pd_03 a06 twi0_sda r01 adc1_vin09 m18 jtg_tms/swdio v02 pd_04 b06 usb0_dm n01 adc1_vin10 m17 jtg_trst u01 pd_05 c07 usb0_dp p01 adc1_vin11 l17 pa_00 m03 pd_06 c11 usb0_id p02 byp_a0 e16 pa_01 k01 pd_07 b11 usb0_vbus n02 byp_a1 p16 pa_02 j02 pd_08 a12 vdd_ana0 j18 byp_d0 r12 pa_03 j01 pd_09 c12 vdd_ana1 k18 dac0_vout d16 pa_04 h02 pd_10 a13 vdd_ext c04 dac1_vout r16 pa_05 h01 pd_11 b12 vdd_ext c05 gnd a01 pa_06 g02 pd_12 b13 vdd_ext c15 preliminary technical data rev. prf | page 117 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f gnd b02 pa_07 g01 pd_13 c13 vdd_ext d08 gnd c03 pa_08 g03 pd_14 a14 vdd_ext d09 gnd c14 pa_09 f01 pd_15 b14 vdd_ext d10 gnd h07 pa_10 d01 pe_00 a15 vdd_ext d11 gnd h08 pa_11 d02 pe_01 b16 vdd_ext l03 gnd h09 pa_12 e03 pe_02 a16 vdd_ext r07 gnd j07 pa_13 d03 pe_03 a17 vdd_ext r09 gnd j08 pa_14 a02 pe_04 v17 vdd_ext t04 gnd j09 pa_15 b04 pe_05 v16 vdd_ext t05 gnd k07 pb_00 a03 pe_06 u16 vdd_ext t14 gnd k08 pb_01 b05 pe_07 v15 vdd_ext t15 gnd k09 pb_02 b07 pe_08 u15 vdd_int d07 gnd l07 pb_03 a07 pe_09 u14 vdd_int d12 gnd l08 pb_04 c08 pe_10 v14 vdd_int h03 gnd l09 pb_05 b08 pe_11 t13 vdd_int r08 gnd r11 pb_06 a08 pe_12 v13 vdd_int r10 gnd t03 pb_07 c09 pe_13 v11 vdd_vreg j03 gnd u02 pb_08 b09 pe_14 u11 vref0 h16 gnd v01 pb_09 a09 pe_15 t10 vref1 l16 gnd_ana a18 pb_10 c10 pf_00 u10 vreg_base k03 gnd_ana b17 pb_11 t12 pf_01 v10 gnd_ana c16 pb_12 u13 pf_02 t09 gnd_ana f16 pb_13 u12 pf_03 u09 gnd_ana h11 pb_14 v12 pf_04 v09 table 76. adsp-cm409f 212-ball bga ball assignments (alphabetical by ball name) (continued) ball name ball no. ball name ball no. ball name ball no. ball name ball no. rev. prf | page 118 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 72 shows an overview of sign al placement on the 212-ball csp_bga package. figure 72. 212-ball csp_bga ball configuration 910 81112131415161718 7 56 4 23 1 bottom view a b c d e f g h j k l m n p r t u v a1 ball corner top view v dd_anax (magenta) v dd_ext (red) v dd_int (gray) gnd_ana (green) vref/refcap/byp (yellow) gnd (blue) i/o signals (white) a b c d e f g h j k l m n p r t u v 9 10 8 11 12 13 14 15 16 17 18 7 5 6 4 2 3 1 a1 ball corner preliminary technical data rev. prf | page 119 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f outline dimensions dimensions in figure 73 (for the 120-lead lqfp), figure 74 (for the 176-lead lqfp) and figure 75 (for the 212-ball bga) are shown in millimeters. figure 73. 120-lead low profile quad flat package, exposed pad [lqfp_ep] 1 (sw-120-3) dimensions shown in millimeters 1 for information relating to th e sw-120-3 packages exposed pad, see the table endnote in adsp-cm402f/adsp-cm403f 120-lead lq fp lead assignments on page 108 . 120 60 90 61 31 1 30 91 bottom view (pins up) compliant to jedec standards ms-026-bee-hd * note: exposed pad dimensions are preliminary and for eng grade material only. the pad size may change for volume production material. to maintain compatibility pcb designers must observe the specified keep-out area. 1.45 1.40 1.35 0.15 0.10 0.05 top view (pins down) 91 1 90 31 30 60 61 120 0.23 0.18 0.13 0.40 bsc lead pitch 1.60 max 16.20 16.00 sq 15.80 14.10 14.00 sq 13.90 view a 0.08 coplanarity view a rotated 90 ccw 12 7 0 0.20 0.15 0.09 0.75 0.60 0.45 1.00 ref * exposed pad 5.40 ref 7.675 ref 3.50 ref 0.10 ref u-groove * see note (10 8 mm area) 2.25 ref 3.15 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 seating plane rev. prf | page 120 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f preliminary technical data figure 74. 176-lead low profile quad flat package, exposed pad [lqfp_ep] 1 (sw-176-3) dimensions shown in millimeters 1 for information relating to th e sw-176-3 packages exposed pad, see the table endnote in adsp-cm407f/ADSP-CM408F 176-lead lq fp lead assignments on page 111 . compliant to jedec standards ms-026-bga-hd 0.15 0.10 0.05 0.08 coplanarity 0.20 0.15 0.09 1.45 1.40 1.35 7 0 view a rotated 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc lead pitch 24.10 24.00 sq 23.90 26.20 26.00 sq 25.80 top view (pins down) bottom view (pins up) 1 44 1 44 45 89 88 45 88 132 89 132 176 133 176 133 1.60 max 1.00 ref seating plane view a 5.80 ref 7.56 ref 3.50 ref 3.027 ref 2.225 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. pin 1 * exposed pad 0.10 ref * note: exposed pad dimensions are preliminary and for eng grade material only. the pad size may change for volume production material. to maintain compatibility pcb designers must observe the specified keep-out area. u-groove * see note (12 8 mm area) preliminary technical data rev. prf | page 121 of 122 | august 2014 adsp-cm402f / cm403f/cm407f / cm408f / cm409f figure 75. 212-ball chip scale package ball grid array [csp_bga] (bc-212-1) dimensions shown in millimeters 1.00 bsc 17.00 ref sq 19.10 19.00 sq 18.90 compliant to jedec standards mo-192-aag-2 with exception of the ball count. 1.00 ref a b c d e f g 9 10 8 11 12 13 14 15 16 17 18 7 5 6 4 2 31 bottom view h j k l m n p r t u v detail a top view detail a coplanarity 0.20 0.70 0.60 0.50 ball diameter seating plane a1 ball corner a1 ball corner 1.11 1.01 0.91 1.70 1.51 1.36 0.50 nom 0.45 min rev. prf | page 122 of 122 | august 2014 preliminary technical data ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr11805-0-8/14(prf) adsp-cm402f / cm403f/cm407f / cm408f / cm409f pre release products model temperature range 1, 2 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 61 for the junction temperature (tj) specification wh ich is the only tempe rature specification. 2 these are pre production parts. see eng-grade agreement for details. package description package option processor instruction rate (max) adsp-cm403fbswzeng tbd 120-lead low-profile quad flat package exposed pad sw-120-3 tbd mhz ADSP-CM408Fbswzeng tbd 176-lead low-profile quad flat package exposed pad sw-176-3 tbd mhz adsp-cm409fcbczeng tbd 212-ball ch ip scale package ball grid array bc-212-1 tbd mhz |
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